Academic
Publications
Data Handling Limits of On-Chip Interconnects

Data Handling Limits of On-Chip Interconnects,10.1109/TVLSI.2008.2000255,IEEE Transactions on Very Large Scale Integration Systems,Rohit Singhal,Gwan

Data Handling Limits of On-Chip Interconnects   (Citations: 3)
BibTex | RIS | RefWorks Download
With shrinking feature size and growing integration density in the deep sub-micrometer (DSM) technologies, the global buses are fast becoming the ldquoweakest-linksrdquo in VLSI design. They have large delays and are error-prone. Especially, in system-on-chip (SoC) designs, where parallel interconnects run over large distances, they pose difficult research and design problems. This paper presents a two-fold approach for evaluating the signal and data carrying capacity of on-chip interconnects. In the first approach, the wire is modeled as a linear time invariant (LTI) system and a frequency response is studied. The second approach addresses delay and reliability in interconnects from an information theoretic perspective. Simulation results for an 8-bit-wide bus in 0.1-mum technology are presented for both approaches. The results closely match to a similar optimal bus clock frequency that will result in the maximum data transfer rate. Moreover, this optimal frequency is higher than that achieved by present day designs which accommodate the worst case delays. The first approach achieves this higher transmission rate using ideal signal shapes, instead of square pulses, while the second approach uses coding techniques to eliminate high delay cases to generate a higher transmission rate. It is seen that the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using communication theory, these ldquogoodrdquo signals arriving early can be used to predict/correct the ldquofewrdquo signals that arrive late.
Journal: IEEE Transactions on Very Large Scale Integration Systems - VLSI , vol. 16, no. 6, pp. 707-713, 2008
Cumulative Annual
View Publication
The following links allow you to view full publications. These links are maintained by other sources not affiliated with Microsoft Academic Search.
    • ...As a results these busses and interconnects becoming more sensitive and prone to errors caused by crosstalk and delay faults [7], [8], [9].Reducing the transitions on data buses can reduces the crosstalk and delay faults [4], [5].The coupling capacitance also depends upon the data dependent transitions and the coupling effect will increase or decrease depending upon the relative switching activity between adjacent bus wires [6]...

    A. Sathishet al. Crosstalk reduction technique on data-bus in DSM technology

    • ...There have been several research work on information theoretic analysis of on-chip copper interconnect [4][5][6]...
    • ...It is interpreted as the residual uncertainty in X given the knowledge of Y and it is given by [4]...
    • ...The capacity is defined as the reduction in uncertainty about the input given the channel output [4]...
    • ...The overall capacity of SWCNT bundle interconnects is then given by [4]...
    • ...It is shown that optimal operation frequency at which the data rate is maximum is 70GHz for an 0.5mm SWCNT bundle interconnects compared to 40GHz for an 0.1µm Cu interconnect technology [4][18]...

    Masud H Chowdhury. Information theoretic capacity analysis of single-walled carbon nanotu...

Sort by: