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Keywords
(11)
Carrying Capacity
Communication Theory
Data Handling
Data Transfer
Frequency Response
Long Tail
Vlsi Design
Information Theoretic
Linear Time Invariant
Present Day
System On Chip
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Data Handling Limits of OnChip Interconnects
Data Handling Limits of OnChip Interconnects,10.1109/TVLSI.2008.2000255,IEEE Transactions on Very Large Scale Integration Systems,Rohit Singhal,Gwan
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Data Handling Limits of OnChip Interconnects
(
Citations: 3
)
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Rohit Singhal
,
Gwan Choi
,
Rabi N. Mahapatra
With shrinking feature size and growing integration density in the deep submicrometer (DSM) technologies, the global buses are fast becoming the ldquoweakestlinksrdquo in VLSI design. They have large delays and are errorprone. Especially, in systemonchip (SoC) designs, where parallel interconnects run over large distances, they pose difficult research and design problems. This paper presents a twofold approach for evaluating the signal and data
carrying capacity
of onchip interconnects. In the first approach, the wire is modeled as a
linear time invariant
(LTI) system and a
frequency response
is studied. The second approach addresses delay and reliability in interconnects from an
information theoretic
perspective. Simulation results for an 8bitwide bus in 0.1mum technology are presented for both approaches. The results closely match to a similar optimal bus clock frequency that will result in the maximum
data transfer
rate. Moreover, this optimal frequency is higher than that achieved by
present day
designs which accommodate the worst case delays. The first approach achieves this higher transmission rate using ideal signal shapes, instead of square pulses, while the second approach uses coding techniques to eliminate high delay cases to generate a higher transmission rate. It is seen that the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using communication theory, these ldquogoodrdquo signals arriving early can be used to predict/correct the ldquofewrdquo signals that arrive late.
Journal:
IEEE Transactions on Very Large Scale Integration Systems  VLSI
, vol. 16, no. 6, pp. 707713, 2008
DOI:
10.1109/TVLSI.2008.2000255
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Citation Context
(2)
...As a results these busses and interconnects becoming more sensitive and prone to errors caused by crosstalk and delay faults [
7
], [8], [9].Reducing the transitions on data buses can reduces the crosstalk and delay faults [4], [5].The coupling capacitance also depends upon the data dependent transitions and the coupling effect will increase or decrease depending upon the relative switching activity between adjacent bus wires [6]...
A. Sathish
,
et al.
Crosstalk reduction technique on databus in DSM technology
...There have been several research work on information theoretic analysis of onchip copper interconnect [
4
][5][6]...
...It is interpreted as the residual uncertainty in X given the knowledge of Y and it is given by [
4
]...
...The capacity is defined as the reduction in uncertainty about the input given the channel output [
4
]...
...The overall capacity of SWCNT bundle interconnects is then given by [
4
]...
...It is shown that optimal operation frequency at which the data rate is maximum is 70GHz for an 0.5mm SWCNT bundle interconnects compared to 40GHz for an 0.1µm Cu interconnect technology [
4
][18]...
Masud H Chowdhury
.
Information theoretic capacity analysis of singlewalled carbon nanotu...
References
(24)
Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits
(
Citations: 4
)
Seung Hoon Choi
,
Kaushik Roy
Conference:
Workshop on Electronic Design, Test and Applications  DELTA
, pp. 365369, 2002
Low power couplingbased encoding for onchip buses
(
Citations: 8
)
Maged Ghoneima
,
Yehea I. Ismail
Conference:
IEEE International Symposium on Circuits and Systems  ISCAS
, pp. 325328, 2004
Energyefficient and reliable lowswing signaling for onchip buses based on redundant coding
(
Citations: 16
)
Davide Bertozzi
,
Luca Benini
,
Bruno Riccò
Conference:
IEEE International Symposium on Circuits and Systems  ISCAS
, pp. 9396, 2002
Information Theoretic Capacity of Long Onchip Interconnects in the Presence of Crosstalk
(
Citations: 7
)
Rohit Singhal
,
Gwan S. Choi
,
Rabi N. Mahapatra
Conference:
International Symposium on Quality Electronic Design  ISQED
, pp. 407412, 2006
Businvert coding for lowpower I/O
(
Citations: 560
)
Mircea R. Stan
,
Wayne P. Burleson
Journal:
IEEE Transactions on Very Large Scale Integration Systems  VLSI
, vol. 3, no. 1, pp. 4958, 1995
Sort by:
Citations
(3)
Crosstalk reduction technique on databus in DSM technology
A. Sathish
,
M. Madhavi Latha
,
K. Lal Kishore
,
K. Kameswara Reddy
Conference:
International Conference on Signal Processing, Communication, Computing and Networking Technologies  ICSCCN
, 2011
Compact model for carbon nanotubes interconnects using fourier series analysis
Suraj Subash
,
M. S. Rahaman
,
Masud H Chowdhury
Conference:
Midwest Symposium on Circuits and Systems  MWSCAS
, pp. 11751178, 2009
Information theoretic capacity analysis of singlewalled carbon nanotube bundle VLSI interconnects
Masud H Chowdhury
Published in 2009.