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Transaction Level Modeling of a Peripheral Using SystemC

Transaction Level Modeling of a Peripheral Using SystemC,Haritha Jillellamudi,Frank Wissinger,Jigisha Goswami,Ravi Shankar

Transaction Level Modeling of a Peripheral Using SystemC  
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Raising the level of abstraction to system level in current SoC design promises to enable faster exploration of the design space at early stages and hence reduce design cycle time. Recently, there has been interest in transaction-level modeling for system abstraction. SystemC 2.0 facilitates the development of Transaction Level Models (TLMs). System architects can quickly develop these models using SystemC and be ready with an executable specification of the design as soon as the initial functional specifications of the system are decided. The high speed of simulation of these TLMs allows early development and verification of hardware dependent application software. Timing details can be incorporated into these models to allow performance estimation and architecture exploration. This paper elaborates in detail above- mentioned TLM concepts and further presents a peripheral modeling at two TLM levels.
Published in 2008.
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