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Foundry workflow for dynamic-EFA-based yield ramp

Foundry workflow for dynamic-EFA-based yield ramp,10.1016/j.microrel.2011.07.079,Microelectronics Reliability,C. Kardach,I. Kapilevich,J. Block,T. Lun

Foundry workflow for dynamic-EFA-based yield ramp  
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The increasing demand for electrical failure analysis (EFA) in yield enhancement [1] has created new challenges for foundries and their clients. Dynamic EFA techniques, more in demand with the smaller technology nodes, have largely been the domain of the design-house failure analysis (FA) lab. In 2010 on 40nm packaged parts, a new laser-based technology, laser voltage imaging (LVI) was applied to shift debug and drove physical failure analysis (PFA) success rate to >90%. This is still the case in 2011 on 28nm ICs. The methodology was validated at the foundry on 32nm wafers and again drove the PFA success rate to >90%. This paper offers a foundry-friendly methodology made possible by LVI and its fast track to the wafer level.
Journal: Microelectronics Reliability , vol. 51, no. 9, pp. 1668-1672, 2011
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