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Serial fault emulation

Serial fault emulation,10.1109/DAC.1996.545681,Luc Burgun,F. Reblewski,G. Fenelon,J. Barbier,O. Lepape

Serial fault emulation   (Citations: 14)
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A hardware emulator based approach has been developed to perform test evaluation on large sequential circuits (at least tens of thousands of gates). This approach relies both on the flexibility and on the reconfigurability of hardware emulators based on dedicated reprogrammable circuits. A Serial Fault Emulation (SFE) method in which each faulty circuit is emulated separately has been applied to gate level circuits for Single Stuck Faults (SSFs). This approach has been implemented on the Meta Systems's hardware emulator which is capable of emulating circuits of 1,000,000 gates at rates varying from 500 kHz to several MHz. Experimental results are provided to demonstrate the efficiency of SFE. They indicate that SFE should be two orders of magnitude faster than sofware approaches for designs containing more than 100000 gates
Conference: Design Automation Conference - DAC , pp. 801-806, 1996
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    • ...One of the first attempts to use logic emulators with fault-injection purposes was proposed in [11] under the name of serial fault emulation...

    David De Andréset al. Fault Emulation for Dependability Evaluation of VLSI Systems

    • ...[9, 10]). The first is to create a complete fault list for the design under test with a selected fault model...
    • ...Inducing faults into a design under test at the selected fault locations is either possible by changing the design’s original function [10] or by introducing fault injectors, sometimes called saboteurs [14]...

    Jan Torben Weinkopfet al. Parsifal: A Generic and Configurable Fault Emulation Environment with ...

    • ...In many of the papers for sequential circuits, faults are injected either by modifying the configuration bitstream while the latter is being loaded into the device [8] or by using partial reconfiguration [9, 10, 11]...

    Jaan Raiket al. Improved Fault Emulation for Synchronous Sequential Circuits

    • ...In many of the papers for sequential circuits, faults are injected either by modifying the configuration bitstream while the latter is being loaded into the device [8] or by using partial reconfiguration [9, 10, 11]...

    Peeter Ellerveeet al. Evaluating Fault Emulation on FPGA

    • ...For example, in the recent Meta Systems approach [25], fault injection was done as in [24], but they used a different FPGA architecture so that they were able to modify only a small portion of the FPGA bit stream without the need for entire reconfiguration; hence, the fault injection time was reduced...
    • ...Thus, fault injection can be made by changing the content of a CLB [24], [25]...
    • ...If partial reconfiguration is available, then the fault injection time can be reduced, i.e., reconfiguration affects only a few CLB’s [25]...
    • ...In [24] and [25], where reconfiguration is required for every fault (or fault group) injection, the fault emulation time thus becomes...
    • ...The first term in (3) usually degrades the overall performance since can be as high as several milliseconds [24], [25]...
    • ...As opposed to previous methods [24], [25], we perform fault injection directly on the original circuit instead of the corresponding CLB, so all faults to be simulated can be stored in the fault-injectable circuit before the FPGA bit stream is generated, i.e., bitstream regeneration is not necessary, and the emulation time is greatly reduced...

    Shih-arn Hwanget al. Sequential circuit fault simulation using logic emulation

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