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ECL-CMOS logic LSI technology using 20 GHz latch with CMOS test circuits

ECL-CMOS logic LSI technology using 20 GHz latch with CMOS test circuits,Atmospheric Environment,S. Yabuki,A. Hayashi,Y. Ito,T. Maruyama,H. Okada,M. U

ECL-CMOS logic LSI technology using 20 GHz latch with CMOS test circuits  
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An ECL-CMOS LSI for computing and communication including 280k ECL gates and 1Mbit RAM is developed with Advanced CMOS ECL Technology, which uses seven layer metallization including copper damascene and SGI/U-Isolation with SOI wafer. Used latch with CMOS test circuits has 20GHz toggle frequency and highly detectable delay test is possible.
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