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HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications

HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications,10.1109/DATE.2003.1253797,Hans-Joachim Stolberg,Mla

HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications   (Citations: 11)
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The HiBRID-SoC multi-core system-on-chip targets a wide range of application fields with particularly high processing demands, including general signal processing applications, video and audio de-/encoding, and a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 µm 6LM standard-cell technology, occupies about 82 mm2 , and operates at 145 MHz.
Conference: Design, Automation, and Test in Europe - DATE , pp. 20008-20013, 2003
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    • ...978-1-4244-9474-3/11/$26.00 ©2011 IEEE 2557 In the specialized multi-core architecture described in [10] a DSP-, RISC- and VLIW-core are connected by a 64-bit AMBA AHB bus...
    • ...The work in [10] shows some relevance regarding the hardware configurations used and described in this paper...

    Christian Stoifet al. Hardware synchronization for embedded multi-core processors

    • ...[9] presents a useful multi-core architecture for multimedia processing applications, which segments general multimedia tasks into steam-oriented, block-oriented, and DSP-oriented functions...

    Yung-Sung Huanget al. Architecture for video coding on a processor with an ARM and DSP cores

    • ...An embedded system containing this VLIW architecture would also include a RISC to control the en-/decoding process, like in [8]...

    Guillermo Paya-Vayaet al. A forwarding-sensitive instruction scheduling approach to reduce regis...

    • ...In order to offer more flexibility than the previous approaches which focus only to a single application, the authors have been proposing domain-specific memory subsystems [9], [13]–[15], [17]...
    • ...The authors published this particular case in [9]...
    • ...As we have seen from the prior work, to enable that, authors organize pixels in narrow memory banks which are single pixel wide [9], [13]–[15], [17]...
    • ...The architectures proposed in [9], [13]–[15], [17] use only one level of memory hierarchy...

    Aleksandar Bericet al. Memory-Centric Video Processing

    • ...With the rapid increase of the transistor budget that is available on chips [34], DSP chip multi-processors are beginning to surface [46, 47] and it is to be expected that this trend is going to continue...
    • ...SMT processors with many TUs need also a larger number of FUs to reach appropriate performance levels, and worse, large register files and instruction windows with many read and write ports for all the FUs [47]...

    Mladen Berekovicet al. A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clus...

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