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Drain Induced Barrier Lowering

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Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers

Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers,10.1109/VLSIT.2003.1221122,S. Choi,D. H. Lee,J. R. Yoo,B. C. Lee,J. Y. Kim,C. G.

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Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers (Citations: 33)


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Nano scale body-tied FinFETs have been firstly fabricated. They have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 60 nm. This Omega MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower ISUB/ID than planar type DRAM cell transistors.

Conference: VLSI Technology, Symposium - VLSIT , 2003

DOI: 10.1109/VLSIT.2003.1221122

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Citation Context (15)

- ...While FinFETs were originally developed on Silicon-on-Insulator (SOI) substrates, the concept has also been adapted to bulk silicon wafers [2]...
E. Simoen, et al. Low-frequency noise in triple-gate n-channel bulk FinFETs
- ...To avoid the need for costly silicon-on-insulator substrates or complex fabrication processes [16], [17], the quasiplanar bulk MOSFET design (Fig. 1) was recently proposed [18]...
Changhwan Shin, et al. Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology fo...
- ...This explains the large research interest in recent years in these devices [1], [2]...
Maria Glória Caño de Andrade, et al. Comparison of the Low-Frequency Noise of Bulk Triple-Gate FinFETs With...
- ...Finally, our model can be used also for bulk FinFET devices [45] and can be easily extended to estimate the permanent leakage current induced by heavy-ion strikes in flash memories FinFET-based, like FinFLASH and FinFET SONOS flash memories [46], [47], and the degradation induced by microdose in high-voltage tolerant devices FinFET-based, like super-junction FinFETs [48]...
Alessio Griffoni, et al. A Statistical Approach to Microdose Induced Degradation in FinFET Devi...
- ...To avoid the need for expensive SOI substrates or more complex fabrication processes [6, 7], the segmented bulk MOSFET (SegFET) design was proposed to reduce VTH variation [8-9]...
Changhwan Shin, et al. Full 3D Simulation of 6T-SRAM Cells for the 22nm Node

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Keywords (1)

Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers,10.1109/VLSIT.2003.1221122,S. Choi,D. H. Lee,J. R. Yoo,B. C. Lee,J. Y. Kim,C. G.

Citation Context (15)

E. Simoen, et al. Low-frequency noise in triple-gate n-channel bulk FinFETs

Changhwan Shin, et al. Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology fo...

Maria Glória Caño de Andrade, et al. Comparison of the Low-Frequency Noise of Bulk Triple-Gate FinFETs With...

Alessio Griffoni, et al. A Statistical Approach to Microdose Induced Degradation in FinFET Devi...

Changhwan Shin, et al. Full 3D Simulation of 6T-SRAM Cells for the 22nm Node

Citations (33)

Low-frequency noise in triple-gate n-channel bulk FinFETs (Citations: 1)

Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22-nm Node

Comparison of the Low-Frequency Noise of Bulk Triple-Gate FinFETs With and Without Dynamic Threshold Operation

A Statistical Approach to Microdose Induced Degradation in FinFET Devices (Citations: 3)

Full 3D Simulation of 6T-SRAM Cells for the 22nm Node (Citations: 1)


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