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Low cost 65nm CMOS platform for Low Power & General Purpose applications

Low cost 65nm CMOS platform for Low Power & General Purpose applications,10.1109/VLSIT.2004.1345363,F. Arnaud,B. Duriez,B. Tavel,L. Pain,J. Todeschini

Low cost 65nm CMOS platform for Low Power & General Purpose applications   (Citations: 16)
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F. Arnaud, B. Duriez, B. Tavel, L. Pain, J. Todeschini, M. Jurdit, Y. Laplanche, F. Boeuf, F. Salvetti, D. Lenoble, J. P. Reynard, F. Wacquanthttp://academic.research.microsoft.com/io.ashx?type=5&id=50374049&selfId1=0&selfId2=0&maxNumber=12&query=
A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 μm2 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully working 0.5 μm2 bit-cells with 240mV of SNM and 35 μA of cell current at 1.2V operation were obtained. The GP transistor drive currents of 875 μA/ μm and 400 μA/ μm for NMOS and PMOS respectively are obtained at Vdd = 1V, Ioff = 100nA/um. Using the same CMOS flow, 65nm analog transistor parameters are derived for the first time, showing Vt matching (Avt=2.2mV. μm) and analog voltage gain factor (Gm/Gd>2000 for L = 10 μm) at the leading edge for this process technology. NBTI criteria at 125°C for both LP and GP transistors are presented and characterized at overdrive conditions.
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    • ...The development is occurring simultaneously in 130 nm SiGe BiCMOS [1] with greater than 230/300 GHz, and 65 nm CMOS [2] with up to 180/270 GHz...

    Sean T. Nicolsonet al. Single-Chip W-band SiGe HBT Transceivers and Receivers for Doppler Rad...

    • ...• �S�E�@�P�DH�.�A�J�C�P�D [8]. Monte Carlo simulations of a standard Master Slave Flip-flop with local within-die variation indicates maximum mismatch of 4 ps in the setup times at the rise time of 1 FO4 delay for the core and sampling clocks...

    Pratap Kumar Daset al. On-chip clock network skew measurement using sub-sampling

    • ...[26]. By comparison, a receiver has been fabricated using STMicroelectronics 65nm GP CMOS [27]...

    Patrice Garciaet al. Will BiCMOS stay competitive for mmW applications ?

    • ...Using the information on transistor widths, we calculate the layout area from previous layouts of each SRAM architecture [4][5][11]...

    Gregory K. Chenet al. Yield-driven near-threshold SRAM design

    • ...Inthis paper, bothconventional andinnovative methods n arepresented andevaluated through acharacterization ofour _ 65nmprocess [3]...
    • ...1&3), while a WLN w voltage sweepisapplied onBLT (from VddtoOV)...
    • ...Write-Margin "true" value (Fig. 3)...
    • ...Fig. 3.Bit-Line Monitored currents during theconventional Write-Margin extraction onBLTside...
    • ...Itfollows the simulations, showed that aparasitic capacitance oflpFon same testchronology thanconventional methodology as internal nodeinduces adelay inthecell flip phase, leading, described infigure 3.Asconventional method, themonitored forinstance, toa4OmVshift inwrite-margin fora1.2Vpower current during aWritecycle ontheBLTside isthecurrent supply (upto8OmVshift fora3pFparasitic capacitance)...
    • ...1.2 54.3 323.2 Itisalsonoticing that better dispersion values areobtained...

    N. Gierczynskiet al. A New Combined Methodology for Write-Margin Extraction of Advanced SRA...

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