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Next generation on-board SAR processor for compact airborne systems

Next generation on-board SAR processor for compact airborne systems,10.1109/IGARSS.2004.1368709,N. Nolte,C. Simon-Klar,S. Langemeyer,M. Kirscht,P. Pir

Next generation on-board SAR processor for compact airborne systems   (Citations: 1)
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A new generation of on-board SAR processors for compact airborne systems is presented, which is currently under development at the Laboratorium für Informationstechnologie (LfI), Universität Hannover. The processor uses the ωk-algorithm (also known as the wavenumber domain algorithm) and features region of interest support and source coding of the SAR images for further reduction of the output data rate. This is important for data transmission via radio data links. The hardware architecture of the SAR processor is based on the HiBRID-SoC, a new signal processor with three fully programmable cores. This SoC allows the mapping of the whole SAR processing chain to a single chip. This reduces the number of hardware components, which is important for the realization of compact and power efficient hardware design.
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