Academic
Publications
A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology

A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology,10.1109/VLSIT.2006.1705236,J. Yuan,S. S. Tan,Y. M. Lee,J. Kim,R. L

A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology   (Citations: 5)
BibTex | RIS | RefWorks Download
J. Yuan, S. S. Tan, Y. M. Lee, J. Kim, R. Lindsay, V. Sardesai, T. Hook, R. Amos, Z. Luo, W. Lee, S. Fang, T. Dyerhttp://academic.research.microsoft.com/io.ashx?type=5&id=50495961&selfId1=0&selfId2=0&maxNumber=12&query=
Device performance has been boosted by integrating dual-stress-liners (DSL) in a 45nm low power platform as a cost effective approach. A stress-proximity-technique (SPT) has been explored to improve device performance without adding process complexity. Record drain currents of 840/490 muA/mum have been achieved for NMOS and PMOS, respectively, at 1.2V and off-leakage current of 1nA/mum. Junction profiles have been optimized to reduce the gate-induced-drain-leakage (GIDL). An asymmetric IO has been integrated into this low power technology for the first time, offering multiple advantages including low cost, performance gain up to 30% and reliability improvement as well
Cumulative Annual
View Publication
The following links allow you to view full publications. These links are maintained by other sources not affiliated with Microsoft Academic Search.
Sort by: