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Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process Window

Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process Window,10.1109/VLSIT.2007.4339692,A. Veioso,P. Verheyen,R. Vos,S. Brus,S. Ito,R. Mi

Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process Window   (Citations: 1)
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A. Veioso, P. Verheyen, R. Vos, S. Brus, S. Ito, R. Mitsuhashi, V. Paraschiv, X. Shi, B. Onsia, S. Arnauts, R. Loo, A. Lauwershttp://academic.research.microsoft.com/io.ashx?type=5&id=50582386&selfId1=0&selfId2=0&maxNumber=12&query=
We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-VT NMOS and PMOS devices with 725/370 muA/mum (at VDD=1.1 V, Ioff=20 pA/mum and Jg= 100/1 mA/cm2). We demonstrate that adding embedded Si0.75Ge0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the VT distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni31Si12 or Ni2Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: -shifting up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; -extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.
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