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Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases,10.1109/VLSIT.2007.4339710,H. Y. Yu,S. Z. Chang,A. Veloso,A.

Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases   (Citations: 10)
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H. Y. Yu, S. Z. Chang, A. Veloso, A. Lauwers, C. Adelmann, B. Onsia, S. Van Elshocht, R. Singanamalla, M. Demand, R. Vos, T. Kauerauf, S. Brushttp://academic.research.microsoft.com/io.ashx?type=5&id=50582404&selfId1=0&selfId2=0&maxNumber=12&query=
This paper reports a novel approach to implement low Vt Ni-FUSI bulk CMOS by using a dysprosium oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5 Aring) can lower the NiSi FUSI nFET Vt by 300 mV/500 mV on HfSiON/SiON (resulting in a Vt,lin of 0.25 V/0.18 V respectively), w/o compromising the Tinv (<1 Aring variation), gate leakage, mobility or reliability. We observed that the DyO cap on SiON can convert into a DySiON silicate with similar electrical properties as HfSiON but much lower Vt, greatly-improved PBTI and 150times lower Jg wrt SiON. By demonstrating a novel DyO cap layer selective removal process, this work also points out the feasibility to realize low Vt CMOS using either dual phase (NiSi, Ni32Si12) or single phase (Ni2Si) FUSI gate for both n-and pFETs.
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