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A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13μm CMOS

A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13μm CMOS,10.1109/ISSCC.2008.4523079,Sandeep Gupta,Jose Tellado,Sridhar B

A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13μm CMOS   (Citations: 5)
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Sandeep Gupta, Jose Tellado, Sridhar Begur, Frank Yang, Vishnu Balan, Michael Inerfield, Dariush Dabiri, John Dring, Sachin Goel, Kumaraguru Muthukumaraswamy, Frank McCarthy, Glenn Goldenhttp://academic.research.microsoft.com/io.ashx?type=5&id=50647595&selfId1=0&selfId2=0&maxNumber=12&query=
A transceiver for IEEE802.3an Ethernet standard, implemented in 0.13mum dual-gate 1.2/2.5V digital CMOS process, consists of a 4-lane AFE running at 800MS/s and a digital processor (DP) in 25x25mm2 BGA package. Power consumption is 10.5W when the transceiver is transmitting and receiving at 10Gb/s over 100m of UTP cable. The transceiver supports interoperability with 100 and 1000Mb/s Ethernet transceivers. The AFE occupies 55mm2 and the DP occupies 150mm2.
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    • ...To that end 10GBASE-T PHYs use advanced signal processing techniques and therefore the circuitry devoted to echo and NEXT cancellation is a significant part of the PHY area and power consumption [8]...
    • ...In Fig. 6 a block diagram of the circuitry used in each of the four pairs in a 10GBASE-T transceiver [8] is shown...
    • ...Echo cancellation is typically done both in the analog domain to reduce the requirements on the Analog to Digital Converter (ADC) and then in the digital domain to eliminate the rest of the echo [8]...
    • ...From the information in [8], savings of 20-30% seem a reasonable estimate...
    • ...Fig. 6. 10GBASE-T circuitry for each twisted pair (from [8])...

    Pedro Reviriegoet al. Using Coordinated Transmission with Energy Efficient Ethernet

    • ...This paper describes a novel DSP based method for canceling nonlinear echo, implemented and tested in a 0.13 µm 10GBASE-T transceiver (previously described in [1]), that reduces the level of the nonlinearity distortion to below 60 dB (for the comparison see Table 1). The whole transceiver implemented in 0.13 µm digital CMOS consisting of AFE and Digital Processor (DP), consumes 10.5 W and occupies...
    • ...The echo of the transmit nonlinearity poised a significant challenge for the design of high speed full-duplex transceivers [1]...
    • ...The 10GBASE-T is the latest generation of Ethernet LAN designed to operate over 100m of CAT6-A structured cabling [4].For proper operation of a 10GBASE-T transceiver, better than 60 dB cancellation of the echo signal is required [1]...
    • ...[1]. In order to be able to amplify the receive signal without overdriving the ADC, it is desirable to attenuate the echo signal before it reaches to the ADC...
    • ...Active echo cancellation allows significant reduction of the echo signal (better than 20dB [1]) in the presence of worst case return loss...
    • ...As shown in Fig. 5.5.5 [1], the SFDR of the transmit signal drops to 56 dB at high frequencies...
    • ...Measurement results of the chip show that SFDR of better than 70 dB at low frequencies (below 75 MHz) and close to 56 dB at 400 MHz (see Fig. 5.5.5 [1])...

    Dariush Dabiriet al. DSP based cancellation of the afe nonlinear echo for 10GBASE-T transce...

    • ...In [3] 40 Gb/s link dissipating 115 mW (2.87 mW/Gb/s) has been proposed while in [4] 10 Gb/s transceiver for 100m UTP-5 copper wire is dissipating 10.5W...

    B. Mooreet al. Chip to chip communications for terabit transmission rates

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