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System in package with mounted capacitor for reduced parasitic inductance in voltage regulators

System in package with mounted capacitor for reduced parasitic inductance in voltage regulators,10.1109/APEC.2008.4522720,T. Hashimoto,T. Kawashima,T.

System in package with mounted capacitor for reduced parasitic inductance in voltage regulators   (Citations: 2)
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A system in package (SiP) on which an input capacitor is mounted has been developed for voltage regulators. The SiP offers the world's lowest power dissipation of 3.8 W at 1 MHz. Its parasitic inductance is 44% lower than SiPs with the input capacitor mounted on the PCB, due to a small loop from the input capacitor to the MOSFETs, which reduces power dissipation by 25% at the same peak voltage. The high-side MOSFET die is flipped so that the drain electrode faces up, facilitating the connection of the MOSFET to the input capacitor. The lead frames and MOSFETs are connected with Cu leads, which reduce the spreading resistance of the MOSFET electrodes.
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