Sign in
Author

Conference

Journal

Organization

Year

DOI
Look for results that meet for the following criteria:
since
equal to
before
between
and
Search in all fields of study
Limit my searches in the following fields of study
Agriculture Science
Arts & Humanities
Biology
Chemistry
Computer Science
Economics & Business
Engineering
Environmental Sciences
Geosciences
Material Science
Mathematics
Medicine
Physics
Social Science
Multidisciplinary
Keywords
(5)
Compact Model
Digital Circuits
Digital Logic
Parameter Extraction
Performance Estimation
Subscribe
Academic
Publications
Physicsbased compact model of IIIV heterostructure FETs for digital logic applications
Physicsbased compact model of IIIV heterostructure FETs for digital logic applications,10.1109/IEDM.2008.4796841,S. Oh,H.S. P. Wong
Edit
Physicsbased compact model of IIIV heterostructure FETs for digital logic applications
(
Citations: 5
)
BibTex

RIS

RefWorks
Download
S. Oh
,
H.S. P. Wong
A physicsbased analytical
compact model
of InGaAs FETs for logic applications is developed. This model neither heavily depends on
parameter extraction
nor requires any timeconsuming computation, enabling digital
circuit design
and circuitlevel
performance estimation
for IIIV FETs. The model captures SCE, trapezoidal well QW energies and capacitances including 2D potential profile information.
Conference:
International Electron Devices Meeting  IEDM
, pp. 14, 2008
DOI:
10.1109/IEDM.2008.4796841
Cumulative
Annual
View Publication
The following links allow you to view full publications. These links are maintained by other sources not affiliated with Microsoft Academic Search.
(
ieeexplore.ieee.org
)
(
ieeexplore.ieee.org
)
Citation Context
(5)
...In a previous paper, we described the physicsbased III–V FET compact model that is distinguished with other models by the minimization of both the number of fitting parameters and computation time [
5
], [6]...
...In this paper, we introduce salient device model features such as gate leakage current and parasitic capacitance in conjunction with the III–V FET compact model presented in [
5
], [6]...
...The compact model encompasses shortchannel effects, fieldconfined and spatially confined quantum well energies, fielddependent ballistic ratio, and capacitances including 2D potential profile information [
5
], [6]...
Saeroonter Oh
,
et al.
PhysicsBased Compact Model for III–V Digital Logic FETs Including Gat...
...Although earlier works have relied on empirical models [
12
], [13], this is the first time that subband energies that treat wavefunction penetration and effective mass discontinuity are analytically described in a compact modeling work...
Sivakumar Mudanai
,
et al.
Capacitance Compact Model for Ultrathin LowElectronEffectiveMass Ma...
...In [
6
], we described the III–V FET compact model and demonstrated its application of circuitlevel performance estimation by simulation of Lg = 20 nm FO4 inverter chains...
...The compact model encompasses short channel effects, field and spatially confined quantum well energies, biasdependent quasiballistic ratio, and capacitance characteristics [
6
], [13]...
Saeroonter Oh
,
et al.
Viability Study of AllIII–V SRAM for Beyond22nm Logic Circuits
...In [
5
, 6], we described the IIIV FET compact model and demonstrated its application of circuitlevel performance estimation by simulation of Lg=20nm FO4 inverter chains...
...The model in [
5
, 6] encompasses short channel effects, field and spatiallyconfined quantum well energies, and capacitances including 2D potential profile information...
Saeroonter Oh
,
et al.
Modeling and analysis of IIIV logic FETs for devices and circuits: Su...
...In order to enable digital circuit design and logic performance estimation for future technology nodes, a compact model of III–V FETs targeted for digital applications is required [
6
]...
Saeroonter Oh
,
et al.
A PhysicsBased Compact Model of III–V FETs for Digital Logic Applicat...
References
(10)
Performance evaluation of 50 nm In/sub 0.7/Ga/sub 0.3/As HEMTs for beyondCMOS logic applications
(
Citations: 20
)
DaeHyun Kim
,
J. A. del Alamo
,
JaeHak Lee
,
KwangSeok Seo
Conference:
International Electron Devices Meeting  IEDM
, 2005
Metal(n) AlGaAsGaAs twodimensional electron gas FET
(
Citations: 104
)
D. Delagebeaudeuf
,
N. T. Linh
Journal:
IEEE Transactions on Electron Devices  IEEE TRANS ELECTRON DEVICES
, vol. 29, no. 6, pp. 955960, 1982
High Mobility IIIV MOSFETs For RF and Digital Applications
(
Citations: 13
)
M. Passlack
,
P. Zurcher
,
K. Rajagopalan
,
R. Droopad
,
J. Abrokwah
,
M. Tutt
,
Y.B. Park
,
E. Johnson
,
O. Hartin
,
A. Zlotnicka
,
P. Fejes
,
R. J. W. Hill
http://academic.research.microsoft.com/io.ashx?type=5&id=50616043&selfId1=0&selfId2=0&maxNumber=12&query=
Conference:
International Electron Devices Meeting  IEDM
, 2007
A Simulation Study of the Switching Times of 22 and 17nm GateLength SOI nFETs on High Mobility Substrates and Si
(
Citations: 14
)
Steven E. Laux
Journal:
IEEE Transactions on Electron Devices  IEEE TRANS ELECTRON DEVICES
, vol. 54, no. 9, pp. 23042320, 2007
Analytical threshold voltage model for short channel n+p+ doublegate SOI MOSFETs
(
Citations: 39
)
K. Suzuki
,
Y. Tosaka
,
T. Sugii
Journal:
IEEE Transactions on Electron Devices  IEEE TRANS ELECTRON DEVICES
, vol. 43, no. 5, pp. 732738, 1996
Sort by:
Citations
(5)
PhysicsBased Compact Model for III–V Digital Logic FETs Including Gate Tunneling Leakage and Parasitic Capacitance
(
Citations: 1
)
Saeroonter Oh
,
H.S. Philip Wong
Journal:
IEEE Transactions on Electron Devices  IEEE TRANS ELECTRON DEVICES
, vol. 58, no. 4, pp. 10681075, 2011
Capacitance Compact Model for Ultrathin LowElectronEffectiveMass Materials
Sivakumar Mudanai
,
Ananda Roy
,
Roza Kotlyar
,
Titash Rakshit
,
Mark Stettler
Journal:
IEEE Transactions on Electron Devices  IEEE TRANS ELECTRON DEVICES
, vol. 58, no. 12, pp. 42044211, 2011
Viability Study of AllIII–V SRAM for Beyond22nm Logic Circuits
Saeroonter Oh
,
H.S. Philip Wong
Journal:
IEEE Electron Device Letters  IEEE ELECTRON DEV LETT
, vol. 32, no. 7, pp. 877879, 2011
Modeling and analysis of IIIV logic FETs for devices and circuits: Sub22nm technology IIIV SRAM cell design
Saeroonter Oh
,
S. Simon Wong
,
H.S. Philip Wong
Conference:
International Symposium on Quality Electronic Design  ISQED
, pp. 342346, 2010
A PhysicsBased Compact Model of III–V FETs for Digital Logic Applications: Current–Voltage and Capacitance–Voltage Characteristics
(
Citations: 4
)
Saeroonter Oh
,
H.S. Philip Wong
Journal:
IEEE Transactions on Electron Devices  IEEE TRANS ELECTRON DEVICES
, vol. 56, no. 12, pp. 29172924, 2009