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Physics-based compact model of III-V heterostructure FETs for digital logic applications

Physics-based compact model of III-V heterostructure FETs for digital logic applications,10.1109/IEDM.2008.4796841,S. Oh,H.-S. P. Wong

Physics-based compact model of III-V heterostructure FETs for digital logic applications   (Citations: 5)
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A physics-based analytical compact model of InGaAs FETs for logic applications is developed. This model neither heavily depends on parameter extraction nor requires any time-consuming computation, enabling digital circuit design and circuit-level performance estimation for III-V FETs. The model captures SCE, trapezoidal well QW energies and capacitances including 2D potential profile information.
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    • ...In a previous paper, we described the physics-based III–V FET compact model that is distinguished with other models by the minimization of both the number of fitting parameters and computation time [5], [6]...
    • ...In this paper, we introduce salient device model features such as gate leakage current and parasitic capacitance in conjunction with the III–V FET compact model presented in [5], [6]...
    • ...The compact model encompasses short-channel effects, field-confined and spatially confined quantum well energies, field-dependent ballistic ratio, and capacitances including 2-D potential profile information [5], [6]...

    Saeroonter Ohet al. Physics-Based Compact Model for III–V Digital Logic FETs Including Gat...

    • ...Although earlier works have relied on empirical models [12], [13], this is the first time that subband energies that treat wavefunction penetration and effective mass discontinuity are analytically described in a compact modeling work...

    Sivakumar Mudanaiet al. Capacitance Compact Model for Ultrathin Low-Electron-Effective-Mass Ma...

    • ...In [6], we described the III–V FET compact model and demonstrated its application of circuit-level performance estimation by simulation of Lg = 20 nm FO4 inverter chains...
    • ...The compact model encompasses short channel effects, field and spatially confined quantum well energies, biasdependent quasi-ballistic ratio, and capacitance characteristics [6], [13]...

    Saeroonter Ohet al. Viability Study of All-III–V SRAM for Beyond22-nm Logic Circuits

    • ...In [5, 6], we described the III-V FET compact model and demonstrated its application of circuit-level performance estimation by simulation of Lg=20nm FO4 inverter chains...
    • ...The model in [5, 6] encompasses short channel effects, field- and spatially-confined quantum well energies, and capacitances including 2D potential profile information...

    Saeroonter Ohet al. Modeling and analysis of III-V logic FETs for devices and circuits: Su...

    • ...In order to enable digital circuit design and logic performance estimation for future technology nodes, a compact model of III–V FETs targeted for digital applications is required [6]...

    Saeroonter Ohet al. A Physics-Based Compact Model of III–V FETs for Digital Logic Applicat...

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