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Uncertainty and reliability analysis of chip scale package subjected to Board-level Drop test

Uncertainty and reliability analysis of chip scale package subjected to Board-level Drop test,10.1109/ESIME.2009.4938466,Masafumi Sano,Chan-Yen Chou,T

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Uncertainty and reliability analysis of chip scale package subjected to Board-level Drop test  
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The board level drop test is intended to evaluate and compare the drop performance of surface mount electronic components. The JEDEC standardize for board level drop test address test board construction, design, material, component locations and test conditions etc. However, in actual drop test conditions, continued drops usually loosen up the mounting screw, which is not considered in JEDEC. This situation may cause the poor repeatability of the experiment. The uncertainty condition of the screw may consequently influence the dynamic behavior of the printed circuit board (PCB) assembly. Accordingly, the drop induced stress in solder joints may be influenced by the tightness of the screw. The objective of this research is to study the uncertainty of the screw condition in relation to the dynamic response on the board level drop test by LS-DYNA3D. Both drop test experiments and dynamic simulation are executed. The modified input-G method, which considered the residuals of screw, was proposed to discuss the uncertainty of screw condition. Residual stress is applied in the tight screw condition. The result shows that a loose screw condition has higher first vibration amplitude of strain, and the vibration frequency is smaller than in a tight screw condition. It is also found that the chip scale package under the loose screw condition has worse reliability in the of drop test due to higher vibration magnitude.
Conference: Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE - EuroSimE , 2009
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