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A 43.7mW 96GHz PLL in 65nm CMOS

A 43.7mW 96GHz PLL in 65nm CMOS,10.1109/ISSCC.2009.4977415,Kun-Hung Tsai,Shen-Iuan Liu

A 43.7mW 96GHz PLL in 65nm CMOS   (Citations: 4)
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In this paper, a 96 GHz PLL, implemented in 65 nm CMOS, is presented that target W-band applications. PLL is composed of a VCO, a low-power divider chain with the division ratio of 256, a PFD, a charge pump (CP), and a 2nd-order loop filter (LF). In the VCO design, a symmetric inductor and a cross-coupled pair are adopted to achieve a high oscillation frequency and a low power consumption.For the divider chain, the four different divider topologies are adopted in a descendant order of the frequency.
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    • ...A number of W-band frequency synthesis techniques have been recently realized in SiGe BiCMOS [2] and CMOS [3-4] technologies...
    • ...It is, however, extremely challenging to achieve the ideal scaling for method three due to the impact of parasitic capacitances and large device noise at W-band, as corroborated in [2] and [4]...

    Zhiming Chenet al. W-band frequency synthesis using a Ka-band PLL and two different frequ...

    • ...Fortunately, recent advances in deep-scaled CMOS technology make it feasible to realize ~100GHz millimeter-wave integrated circuits operating with >180GHz fT devices [1], which has been recently exemplified by a fixed division ratio PLL in [2]...
    • ...[2] is primarily due to its much wider frequency coverage and extra integration of phase rotators and T/R LO buffers...

    Zhiwei Xuet al. An integrated frequency synthesizer for 81–86GHz satellite communicati...

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