Custom design in a low-power/high-performance ASIC world

Custom design in a low-power/high-performance ASIC world,10.1109/ICICDT.2009.5166251,T. Garibay,R. Reis

Custom design in a low-power/high-performance ASIC world   (Citations: 1)
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Aggressive design cycle requirements are making it increasingly difficult to deploy custom and even semi-custom design techniques in consumer ASIC's. However, market requirements continue to push IP implementation teams harder and harder for increased performance and reduced power consumption. Given these two conflicting trends, new design methodologies are required, such that IP design teams can meet market expectations, without the large staffs and long schedules that have traditionally characterized custom design. This presentation reviews several high-ROI methodologies which can be utilized in this design environment to improve implementations without dramatic impact to budgets and schedules.
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    • ...While other discussions of semi-custom design flows highlight the improved timing [1], lower power [2], and better area [3] of custom placement, together with the design efficiency of today’s automated Place and Route tools handling the detailed routing work, these discussions typically cover only regular memory structures, or tiling of regular slices of standard CMOS cells...

    David Kiddet al. High Productivity Circuit Methodology for a Semi-Custom Embedded Proce...

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