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Partially reconfigurable interconnection network for dynamically reprogrammable resource array

Partially reconfigurable interconnection network for dynamically reprogrammable resource array,10.1109/ASICON.2009.5351593,Muhammad Ali Shami,Ahmed He

Partially reconfigurable interconnection network for dynamically reprogrammable resource array   (Citations: 7)
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This paper describes an innovative regular non-blocking, point-to-point, point-to-multipoint, low latency interconnection network scheme with sliding window connectivity, which allows arbitrary parallelism among large sub-systems. The area overhead of interconnect is only 30% of the chip area which is much smaller as compared to 80% in case of FPGA. The interconnection scheme is partially and dynamically reconfigurable. The configware is reduced 5.6 times by using binary encoding which allows energy efficient dynamic reconfiguration.
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