Competitive and cost effective high-k based 28nm CMOS technology for low power applications

Competitive and cost effective high-k based 28nm CMOS technology for low power applications,10.1109/IEDM.2009.5424255,F. Arnaud,A. Thean,M. Eller,M. L

Competitive and cost effective high-k based 28nm CMOS technology for low power applications   (Citations: 5)
BibTex | RIS | RefWorks Download
F. Arnaud, A. Thean, M. Eller, M. Lipinski, Y. W. Teh, M. Ostermayr, K. Kang, N. S. Kim, K. Ohuchi, J.-P. Han, D. R. Nair, J. Lian
In this paper, we present a cost-effective 28 nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm2, and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28 nm from 45 nm technology. Our high-density SRAM bit-cell (area= 0.120mm2) has a demonstrated Static Noise Margin (SNM) of 213 mV at 1 V. Fully compatible with power/leakage management techniques intensively used in low power designs, the transistor drive currents are increased +35% & +10%, for nFET and pFET respectively, with respect to a 28 nm LP poly/SiON reference. Compatible with LP system-on-chip requirements, ultra low-cost, high performance analog devices are reported which leverage a dramatic improvement in matching factor ( versus our previously-reported result. An optimized interconnection scheme based on Extreme Low k (ELK) dielectric (k~2.4) and advanced metallization allows high density wiring with competitive R-C versus our previous technology.
Cumulative Annual
View Publication
The following links allow you to view full publications. These links are maintained by other sources not affiliated with Microsoft Academic Search.
    • ...N ORDER to continue scaling according to Moore’s law, the high-k dielectric and metal gate structure has been introduced to further thin down the gate dielectric without sacrificing gate leakage [3], [4]...
    • ...The thick-Tinv device is different from the core device, inasmuch as it has the silicon dioxide layer inserted to bring Tinv high enough to sustain high operational voltage, which, in this case, is typically 1.8 V. In IBM’s 32-nm platform technology, the gate-first scheme was selected to realize process and layout simplicity and, thus, low fabrication cost [3], [4]...
    • ...DSL technique has already become a standard process in modern CMOS process technology to boost short-channel mobility of NMOS and PMOS [3], [4] for both core and thick-Tinv transistors...
    • ...Semiconductor Research and Development Center 300-mm line using gate-first 32-nm bulk high performance technology, integrating DSL, stress memorization technology, and embedded SiGe S/D on PMOS [3], [4]...

    Qintao Zhanget al. Self-Annealing Effect of Tensile Liner on Thick-Tinv PMOS

    • ...Figure 14 (a) and (b) defines A VT as per Pelgrom (from σΔVT ) [26, 27], (c) defines A VT from σVT (a √ 2 difference...

    Kelin Kuhn. Variability in nanoscale CMOS technology

Sort by: