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Design of A 100MHz – 1.66GHz, 0.13µm CMOS phase locked loop

Design of A 100MHz – 1.66GHz, 0.13µm CMOS phase locked loop,10.1109/ICEDSA.2010.5503082,Mehdi Ayat,Behnam Babaei,Reza Ebrahimi Atani,Sattar Mirzakucha

Design of A 100MHz – 1.66GHz, 0.13µm CMOS phase locked loop  
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A fully integrated charge-pump phase-locked loop (PLL) is described. The PLL is designed and simulated in a 0.13 CMOS technology. The PLL lock range is from 100MHz to 1.66GHz.
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