A fully integrated CMOS GPS receiver with double conversion technique,10.1109/ISSSE.2010.5607079,Chen Ying-mei,Jing Yong-kang,Zhang Zhi-hang,Zhang Li

A fully integrated CMOS GPS receiver with double conversion technique


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This paper presents a L1 band low noise integrated global positioning system (GPS) receiver chip using 0.18-um CMOS technology. Dual-conversion with a low-IF architecture was used for this GPS receiver. The receiver is composed of LNA, down-conversion mixers, band pass filter, received signal strength indicator, variable gain amplifier, programmable gain amplifier, ADC, PLL frequency synthesizer and some other key blocks. The receiver exhibits maximum gain of 105 dB and noise figure of less than 6 dB. The VGA and PGA provide gain control dynamic range over 50 dB. The receiver consumes less than 160 mW from a 1.8-V supply while occupying a 2.9-mm2 chip area including the ESD I/O pads.

Conference: URSI International Symposium on Signals, Systems, and Electronics - ISSSE , 2010

DOI: 10.1109/ISSSE.2010.5607079

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Keywords (9)

A fully integrated CMOS GPS receiver with double conversion technique,10.1109/ISSSE.2010.5607079,Chen Ying-mei,Jing Yong-kang,Zhang Zhi-hang,Zhang Li

References (5)

A Low Noise Figure 1.2-V CMOS GPS Receiver Integrated as a Part of a Multimode Receiver (Citations: 11)

GPS receiver architectures and measurements (Citations: 158)

A CMOS transconductance-C filter technique for very high frequencies (Citations: 231)

The impact of device type and sizing on phase noise mechanisms (Citations: 83)

Design issues in CMOS differential LC oscillators (Citations: 384)


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