Academic
Publications
Maximizing ESD design window by optimizing gate bias for cascoded drivers in 45nm and beyond SOI technologies

Maximizing ESD design window by optimizing gate bias for cascoded drivers in 45nm and beyond SOI technologies,Souvick Mitra,Robert Gauthier,Shunhua Ch

Maximizing ESD design window by optimizing gate bias for cascoded drivers in 45nm and beyond SOI technologies   (Citations: 2)
BibTex | RIS | RefWorks Download
In advanced SOI technologies, the bottom gate voltage plays an important role in achieving the maximum trigger voltage Vt1 of the cascoded drivers. A comparable MOSFET and BJT current handling is needed to ensure maximum Vt1. The minimum and maximum Vt1 window for cascoded driver is shown to range between a single FET Vt1 and twice single FET Vt1.
Published in 2010.
Cumulative Annual
View Publication
The following links allow you to view full publications. These links are maintained by other sources not affiliated with Microsoft Academic Search.
Sort by: