A 40Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset with SFI5 Interface for Optical Transmission Systems
A fully integrated 40-Gb/s transmitter and receiver chipset with SFI-5 interface was implemented in a 65-nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides a good jitter performance with a 40-GHz full-rate clock architecture that alleviates pattern-dependent jitter. The measured RMS jitter on the output was 570 to 900 fs at 39.8 Gb/s to 44.6 Gb/s using a 2^31-1 PRBS pattern. The receiver chip operates at between 37 Gb/s to 41 Gb/s. The measured RMS jitter on the recovered clock was 319 to 450 fs. By taking advantage of CMOS technology, each chip consumes only about 2.8 W of power and is fully integrated with SFI-5 functions, PRBS generators/error checkers and a DPSK precoder/decoder in a 4.9×5.2 mm2 die.