The scan-DFT features of AMD's next-generation microprocessor core

The scan-DFT features of AMD's next-generation microprocessor core,10.1109/TEST.2010.5699203,Mahmut Yilmaz,Baosheng Wang,Jayalakshmi Rajaraman,Tom Ols

The scan-DFT features of AMD's next-generation microprocessor core   (Citations: 1)
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There is an ever-increasing demand for higher performance microprocessors within a given power budget. This demand forces design choices - that were once seen only in high-speed custom blocks - to spread throughout the microprocessor core. These unique design structures, combined with the nanometer technology test challenges such as crosstalk, process variations, power-supply noise, and resistive short and open defects, lead to unique test challenges for today's high-performance microprocessor core. In this paper, we present the scan architecture-related design-for-test (DFT) features and corresponding verification strategies of the nextgeneration Advanced Micro Devices (AMD) high-performance microprocessor core.
Conference: International Test Conference - ITC , pp. 1-10, 2010
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    • ...As explained in [10], the two-latch version of LSSD consists of a two-port latch L I for scan and operation, respectively, and a one-port latch L2 shared by both scan and system operations...
    • ...In reality, a scan chain can have regular flops, low-power flops, and even scannable A-phase latches [10]...
    • ...To further evaluate the new cell, we laid out the new cell, estimated possible yield impact, calculated possible power increase, and analyzed its robustness from a DFM perspective on AMD's next-generation microprocessor core in [10]...

    Baosheng Wanget al. Structural tests of slave clock gating in low-power flip-flop

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