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Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains

Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains,10.1109/TEST.2010.5699211,Tom Waayers,Richar

Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains  
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This paper presents a clock control architecture for designs with multiple clock domains, and a novel mix of existing ATPG techniques as well as novel ATPG enhancements. The combination of the ATPG techniques and the clock control hardware lowers the number of test patterns in a fully automated flow, while maintaining the high coverage that is required nowadays by production test. Experimental results are shown for two industrial designs.
Conference: International Test Conference - ITC , pp. 1-10, 2010
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