Efficient RC power grid verification using node elimination

Efficient RC power grid verification using node elimination,Ankit Goyal,Farid N. Najm

Efficient RC power grid verification using node elimination  
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To ensure the robustness of an integrated circuit, its power distribution network (PDN) must be validated beforehand against any voltage drop on VDD nets. However, due to the increasing size of PDNs, it is becoming difficult to verify them in a reasonable amount of time. Lately, much work has been done to develop Model Order Reduction (MOR) techniques to reduce the size of power grids but their fo- cus is more on simulation. In verification, we are concerned about the safety of nodes, including the ones which have been eliminated in the reduction process. This paper pro- poses a novel approach to systematically reduce the power grid and accurately compute an upper bound on the voltage drops at power grid nodes which are retained. Furthermore, a criterion for the safety of nodes which are removed is es- tablished based on the safety of other nearby nodes and a user specified margin.
Published in 2011.
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