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Processing and reliability analysis of flip-chips with solder bumps down to 30 μm diameter

Processing and reliability analysis of flip-chips with solder bumps down to 30 μm diameter,10.1109/ECTC.2011.5898617,Jorg Franke,Rainer Dohle,Florian

Processing and reliability analysis of flip-chips with solder bumps down to 30 μm diameter  
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The accelerated trend to smaller and lighter electronics has accentuated many efforts towards size reduction and increased performance in electronic products. However, equipment and processes of electronics production have to come along with this trend when it comes to connections on board level. The use of flip-chip bonding technology employing micro bumps for very fine pitch packaging is becoming increasingly important in the microelectronics industry. To meet these requirements, cost-efficient solder bumping and automated assembly technologies for the processing of flip-chips have been developed and qualified. Flip-chips used in this study show a pitch of 100 µm and solder ball diameter of 40 µm and 30 µm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer (WLSST) process and solder sphere jetting (SB²) technology, respectively. The latter is a technique that has been used for many years in the wafer level packaging industry and is commonly known as a solder ball bumping tool. For the described work the SB² technology was scaled down for processing solder spheres with diameters of 30 µm with very good results achieved. Our research has shown that the underfill process is one of the most crucial factors when it comes to flip-chip miniaturization for high reliability applications. Therefore, a total of thirty different underfill materials were investigated initially in terms of flow time, gap height, filler sedimentation, and reliability. For reliability investigations, various standardized test conditions were applied to the test specimen. In previous experiments we found out that solder spheres of 50 µm seem to be the technological limit with current organic printed circuit board technology with subtractive structuring. Therefore, thin film ceramic as substrate material has been used showing excellent performance of the highly miniaturized solder joints at several reliability tests. Concluding long-term reliability and an analysis of the intermetallic growth are shown using SEM/EDX. Additionally, an analysis of the failure mechanism will be presented and recommendations for further miniaturization will be outlined. Advantages of the developed technology are lower cost compared to known techniques, very high flexibility and freedom in selection of solder composition including SAC, low melting alloys, gold-tin, and further special alloys.
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