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Cmos Integrated Circuits
Positive Feedback
Power Consumption
Floating Gate
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A 0.8 V quasi-floating-gate fully differential CMOS op-amp with positive feedback
A 0.8 V quasi-floating-gate fully differential CMOS op-amp with positive feedback,10.1109/ECTICON.2011.5947780,Thawatchai Thongleam,Apirak Suadet,Vara
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A 0.8 V quasi-floating-gate fully differential CMOS op-amp with positive feedback
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Thawatchai Thongleam
,
Apirak Suadet
,
Varakorn Kasemsuwan
This paper presents a 0.8 V fully differential CMOS op-amp. The input stage of the circuit is designed using quasi floating-gate (QFG) transistors with positive feedback, while QFG transistors in the output stage are connected in the class AB configuration. QFG transistors are employed, enabling the circuit to operate under low supply voltage. The proposed amplifier is designed using 0.18 Ilm CMOS technology, and simulation results show rail-to-rail input and output swings. The open-loop gain is 80.4 dB with the gain-bandwidth product of 8.66 MHz. Phase margin is 45° (CL= 20 pF). The CMRR is 107 dB (at 1 kHz) and the
power consumption
is 54.9 IlW.
Conference:
International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology - ECTI-CON
, 2011
DOI:
10.1109/ECTICON.2011.5947780
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