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FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations
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FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations   (Citations: 1)
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FIST (Fast Interconnect Simulation Techniques) is a fast and simple packet latency estimator to replace timeconsuming detailed Network-on-Chip (NoC) models in fullsystem performance simulators. FIST combines ideas from analytical network modeling and execution-driven simulation models. The main idea is to abstractly model each router as a load-delay curve and sum load-dependent delay at each visited router to obtain a packet’s latency by tracking each router’s load at runtime. The resulting latency estimator can accurately capture subtle load-dependent behaviors of a NoC but is much simpler than a full-blown execution-driven model. We study two variations of FIST in the context of a software-based, cycle-level simulation of a tiled chip-multiprocessor (CMP). We evaluate FIST’s accuracy and performance relative to the CMP simulator’s original execution-driven 2D-mesh NoC model. A static FIST approach (trained oine using uniform random synthetic trac) achieves less than 6% average error in packet latency and up to 43x average speedup for a 16x16 mesh. A dynamic FIST approach that adds periodic online training reduces the average packet latency error to less than 2% and still maintains an average speedup of up to 18x for a 16x16 mesh. Moreover, an FPGA-based realization of FIST can simulate 2D-mesh networks up to 24x24 nodes, at 3 to 4 orders of magnitude speedup over software-based simulators.
Published in 2011.
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