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An Evaluation of Selective Depipelining for FPGA-based Energy-Reducing Irregular Code Coprocessors

An Evaluation of Selective Depipelining for FPGA-based Energy-Reducing Irregular Code Coprocessors,10.1109/FPL.2011.16,Jack Sampson,Manish Arora,Natha

An Evaluation of Selective Depipelining for FPGA-based Energy-Reducing Irregular Code Coprocessors  
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