Self-Controlled Writing and Erasing in a Memristor Crossbar Memory

Self-Controlled Writing and Erasing in a Memristor Crossbar Memory,10.1109/TNANO.2011.2166805,IEEE Transactions on Nanotechnology,Idongesit E. Ebong,P

Self-Controlled Writing and Erasing in a Memristor Crossbar Memory  
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The memristor device technology has created waves in the research community and led to the consideration of using the device in multiple avenues. The most likely candidate for early adoption is the nonvolatile memory due to the small cell size (in- creased scaling potential), increased density as compared to flash, and ability to stack these devices in a crossbar structure. This pa- per analyzes the feasibility of a memristor memory and introduces an adaptive read, write, and erase method that may be used to realize a more resilient memory system in the face of low yield in the nanotechnology regime. The proposed method is evaluated in simulation program with integrated circuit emphasis (SPICE) and a hand analysis model is extracted to help explain the sources of power and energy consumption. Finally, the power metrics are compared to flash memory technology, and the memristor memory is shown to have an energy per bit consumption about one-tenth that of flash when programming, comparable to flash when erasing, and about one-fourth of flash when reading. Index Terms—Memristor, resistive random access memory (RAM). memristor's simple structure, small size compared to transistors, and nonvolatility make it a viable candidate for next-generation memory technology. Memristor memory is a subset of resistive memory since logic states are encoded in the memristor's re- sistance. Even though resistive memory is a more general term, some problems associated with resistive memory in a crossbar array are also characteristic to the memristor memory. The dif- ference between resistive memory and memristor memory lies in the fact that memristors have a pinched hysteresis loop at the origin, while the more general term, resistive, includes devices such as the one in (7), which do not possess this trait. Resistive memory in essence comprises a lump of devices with differing resistance-change mechanisms. The method introduced in this paper, hence, may not be applicable to all resistive memory de- vices, but it is definitely advantageous to memristor memory systems. The memristor memory presents a solution to difficulties en- countered beyond CMOS scaling, but it also introduces vari- ous complications to realizing this memory system. The patent database provides a myriad of methods to deal with difficulties (resistance drift, nonuniform resistance profile across the cross- bar array, leaky crossbar devices, etc.) that arise from working with these resistive memory elements. These difficulties (prob- lems) are addressed within the database by using correcting pulses to mitigate effect of resistance drift due to normal us- age (8); using a temperature-compensating circuit to counter resistance drift due to temperature variation (9); using an adap- tive method to read and write to an array with nonuniform resistance profile (10); and introducing diodes (11) or metal- insulator-metal (MIM) diodes to reduce leaky paths within the crossbar memory array (12). With every proposed solution to counter a problem, there are drawbacks that need to be considered. This work exposes a view that will lead to the realization of memristor-based memory in the face of low device yield and the aforementioned problems that plague memristor memory. Section II briefly introduces the memristor, isolating diode, and crossbar modeling employed. Section III describes the reading, writing, and erasing methodol- ogy. Section IV shows the simulation results. Section V explains the results. Section VI provides concluding remarks.
Journal: IEEE Transactions on Nanotechnology - IEEE TRANS NANOTECHNOL , vol. 10, no. 6, pp. 1454-1463, 2011
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