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Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels,10.1109/LED.2011.2107498,IEEE Electron Device Letters,Chun-J

Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels  
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In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) config- uration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications. Index Terms—Accumulation mode, gate all around (GAA), inversion mode (IM), nanowire (NW), thin-film transistor (TFT).
Journal: IEEE Electron Device Letters - IEEE ELECTRON DEV LETT , vol. 32, no. 4, pp. 521-523, 2011
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