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PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models

PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models,10.1109/TCPMT.20

PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models   (Citations: 1)
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The impedance of a power-distribution network (PDN) in three-dimensionally stacked chips with multiple through-silicon-via (TSV) connections (a 3D TSV IC) was modeled and analyzed using a power/ground (P/G) TSV array model based on separated P/G TSV and chip-PDN models at frequencies up to 20 GHz. The proposed modeling and analysis methods for the P/G TSV and chip-PDN are fundamental for estimating the PDN impedances of 3D TSV ICs because they are composed of several chip-PDNs and several thousands of P/G TSV connections. Using the proposed P/G TSV array model, we obtained very efficient analyses and estimations of 3D TSV IC PDNs, including the effects of TSV inductance and multiple-TSV inductance, depending on P/G TSV arrangement and the number of stacked chip-PDNs of a 3D TSV IC PDN. Inductances related to TSVs, combined with chip-PDN inductance and capacitance, created high upper peaks of PDN impedance, near 1 GHz. Additionally, the P/G TSV array produced various TSV array inductance effects on stacked chip-PDN impedance, according to their arrangement, and induced high PDN impedance, over 10 GHz. Index Terms—Power distribution network (PDN), PDN impedance, stacked chip-PDN, through-silicon-via (TSV), TSV array inductance, TSV inductance, three-dimensional (3D), 3D TSV integrated circuit (IC).
Published in 2011.
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    • ...In the paper, through introducing Spice compatible models for signal and power integrity analysis, typical propagation modes in TSV, frequency and time domain electrical performances depending on TSV design, noise coupling mechanism between TSVs, and on-chip PDN impedance variations depending on TSV and stacking designs in 3D IC are explained and shown by referencing to the previous works such as [3-6], which are done by this paper’s...

    Jun So Paket al. Signal and power integrity analysis of TSV-Based 3D IC

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