Academic
Publications
Low Phase Noise and Low Power Consumption VCOs Using CMOS and IPD Technologies

Low Phase Noise and Low Power Consumption VCOs Using CMOS and IPD Technologies,10.1109/TCPMT.2011.2109386,Yuan-Chia Hsu,Hwann-Kaeo Chiou,Hsien-Ku Chen

Low Phase Noise and Low Power Consumption VCOs Using CMOS and IPD Technologies  
BibTex | RIS | RefWorks Download
This paper presents two voltage controlled oscil- lators (VCOs) operating at 5.42 and 5.76 GHz implemented in 0.18-µm complementary metal-oxide semiconductor (CMOS) technology with integrated passive device (IPD) inductors. One IPD inductor was stacked on the top of the active region of the 5.76-GHz VCO chip, whereas the other IPD inductor was placed on the top of the 5.42-GHz VCO CMOS chip but far from the its active region. The high-quality IPD inductors reduce the phase noise of the VCOs. The measurements of the two VCOs indicate the same phase noise of �120 dBc/Hz at 1 MHz offset frequency. These results demonstrate a 6-dB improvement compared to the VCO using an on-chip inductor. This paper also presents the effect of the coupling between the IPD inductor and the active region of the chip on the phase noise performance.
Published in 2011.
Cumulative Annual
View Publication
The following links allow you to view full publications. These links are maintained by other sources not affiliated with Microsoft Academic Search.