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7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS

7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS,10.1109/JSSC.2011.2131730,IEEE Journal of Solid-state Circuits,Masum Hossain,Anthony Chan Ca

7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS  
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A high-frequency jitter tolerant receiver in 65 nm CMOS is presented. Jitter tolerance is improved by tracking cor- related jitter using a pulsed clock forwarded from the transmitter side. The clock receiver comprises two injection locked oscilla- tors to frequency-multiply, deskew, and adjust jitter tracking bandwidth. Different data rates and latency mismatch between the clock and data paths are accommodated by a jitter tracking bandwidth that is controllable up to 300 MHz. Each receiver con- sumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200 MHz. Index Terms—Injection locking, jitter tracking, source syn- chronous.
Journal: IEEE Journal of Solid-state Circuits - IEEE J SOLID-STATE CIRCUITS , vol. 46, no. 6, pp. 1337-1348, 2011
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