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A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking

A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking,10.1109/JSSC.2011.2157259,IEEE Journal of Solid-state Circuits

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A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking   (Citations: 2)
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A digital phase-locked loop (DPLL) employs a linear proportional path, a double integral path, bandwidth and tuning range tracking; and a novel delta-sigma digital to analog converter to achieve low jitter, wide operating range and low power.The pro- posed proportional path decouples the detector quantization error and oscillator noise bandwidth tradeoff and helps maximize band- width to suppress digitally controlled oscillator (DCO) phase noise in a power efficient manner. A double integral path alleviates the tradeoffbetweenDCOtuningrangeanditsfrequencyquantization error. The high resolution of the DCO was maintained over a wide range of sampling clock frequencie sb y using ad elta-sigma digital to analog converter and a continuously tunable switched-RC filter. Bandwidth and tuning range tracking are employed to achieve low jitter over the entire operating range. The prototype DPLL, fabri- catedina90nmCMOSprocess,operatesfrom0.7GHzto3.5GHz. At 2.5 GHz, the proposed DPLL consumes only 1.6 mW power from a 1 V supply and achieves 1.6 ps and 11.6 ps of long-term r.m.s and peak jitter, respectively.
Journal: IEEE Journal of Solid-state Circuits - IEEE J SOLID-STATE CIRCUITS , vol. 46, no. 8, pp. 1870-1880, 2011
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