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Novel Sub10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain

Novel Sub10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain,10.1109/LED.2010.2093557,IEEE Electron Device Letters,Yi-Hsie

Novel Sub10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain  
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We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimen- sion is about 7 × 12 nm. A superior smooth elliptical shape is obtained, for the first time, in the category of poly-Si NW TFTs through the use of a novel fabrication process requiring no advanced lithographic tools. The GAA RSDNW-TFTs ex- hibit low supply gate voltage (3 V), steep subthreshold swing ∼99 mV/dec, and high ION/IOFF > 10 7 (VD = 1V ) without hydrogen-related plasma treatments. Furthermore, the DIBL of GAA RSDNW-TFTs is well controlled. These improvements can be attributed to the 3-D gate controllability, raised S/D struc- ture, and sub-10-nm Si NW channel. These novel GAA RSDNW-TFTs are, thus, quite suitable for system-on-panel and 3-D IC applications. Index Terms—Gate-all-around (GAA), nanowire (NW), poly-Si thin-film transistors (poly-Si TFTs), raised source/drain (S/D).
Journal: IEEE Electron Device Letters - IEEE ELECTRON DEV LETT , vol. 32, no. 2, pp. 173-175, 2011
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