Author | Conference | Journal | Organization | Year | DOI
Look for results that meet for the following criteria:
Academic
Publications
An Ultralow-Power Mixed-Signal Back End for Passive Sensor UHF RFID Transponders

An Ultralow-Power Mixed-Signal Back End for Passive Sensor UHF RFID Transponders,10.1109/TIE.2011.2159695,IEEE Transactions on Industrial Electronics,

Edit
An Ultralow-Power Mixed-Signal Back End for Passive Sensor UHF RFID Transponders  
BibTex | RIS | RefWorks Download
This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency identification transponder in full compliance with the Electronic Product Code Class-1 Generation-2 protocol, defined in the stan- dard ISO 18000-6C. The chip, implemented in a low-cost 0.35-µm CMOS technology process, includes a baseband processor, an analog-to-digital converter (ADC) to digitize the signal acquired from the external sensor, and some auxiliary circuitry for voltage regulation and reference generation. The proposed solution uses two different supply voltages, one for the processor and the other for the mixed-signal circuitry, and defines a novel communication protocol between both blocks so that analog readouts are mini- mally affected by the digital activity of the tag. The whole system was first functionally validated by exhaustively testing with exter- nal dc power supplies ten prototype samples, and then, the two main blocks, processor, and ADC were individually tested to as- sess their performance limits. Regarding the baseband processor, experiments were performed toward the calculation of its packet error rate (PER) under two typical biasing configurations of passive tags, using either crude clamps or regulators. It was found that the regulated biasing outperforms the clamping solution and obtains a PER of 3 × 10 �3 with a supply voltage of 0.75 V. The current consumption of the processor during the reception and response to a Read command at maximum backward rate is only 2.2 µA from a 0.9-V supply. Regarding the ADC, it is a 10-b successive approximation register converter which obtains 9.41 b of effective resolution at 2-kS/s sampling frequency with a power consumption of 250 nW, including the dissipation of a current generation cell and the clock generation circuitry, from 1-V supply. Index Terms—Baseband processing, Electronic Product Code (EPC) Class-1 Generation-2 (Gen2) protocol, ISO 18000-6C, low-power design, passive transponder, radio-frequency (RF) identification (RFID), sensor interface, successive approximation register (SAR) analog-to-digital converter (ADC) (SAR-ADC).
Journal: IEEE Transactions on Industrial Electronics - IEEE TRANS IND ELECTRON , vol. 59, no. 2, pp. 1310-1322, 2012
Cumulative Annual
View Publication
The following links allow you to view full publications. These links are maintained by other sources not affiliated with Microsoft Academic Search.
Share this on