Author | Conference | Journal | Organization | Year | DOI
Look for results that meet for the following criteria:
Academic
Publications
High Productivity Circuit Methodology for a Semi-Custom Embedded Processor

High Productivity Circuit Methodology for a Semi-Custom Embedded Processor,10.1109/TVLSI.2010.2081693,IEEE Transactions on Very Large Scale Integratio

Edit
High Productivity Circuit Methodology for a Semi-Custom Embedded Processor  
BibTex | RIS | RefWorks Download
A high productivity methodology for implementing custom circuitblocksinsideasynthesizedmicroprocessorispresented.Acell-based design style and script-based preroutes are used with a commercial place and route tool, enabling fast layout for custom blocks. The design method- ology supports domino logic, register files, and random logic designs. A semi-custom MIPS microprocessor targeted for the high-volume consumer electronics market is implemented with this methodology. IndexTerms—Designautomation, designmethodology,microprocessors. This paper presents a design methodology used to develop and verify high speed custom digital circuits incorporated in a semi-custom em- bedded MIPS processor targeted for the consumer electronics market. This methodology is targeted toward allowing an essentially full- custom design, including domino logic, non-bitsliced control logic, and multi-port custom register files. The design uses as much automation as possible, which allows development of the custom portions with a very small team. While other discussions of semi-custom design flows highlight the improved timing (1), lower power (2), and better area (3) of custom placement, together with the design efficiency of today's automated Place and Route tools handling the detailed routing work, these discussions typically cover only regular memory structures, or tiling of regular slices of standard CMOS cells. In fact, (4) specifi- cally states that non-regular blocks such as adders do not fit well into a tiling semi-custom approach, and they opt to avoid a full-custom design style in favor of an automated transistor sizing tool, using static CMOS gates and automated placement. This suggests that architectural design choices are determined by the layout automation tools available. The flow presented here can be applied to non-regular control-like circuits, and is applied to a variety of circuit blocks in the microprocessor. An Automated Placement and Routing flow is presented, describing the benefits of a semi-custom schematic based placement flow with pre- routing for critical nets. Tool usage information, pre-layout analysis, and block integration are then summarized. To conclude, results from both the methodology productivity improvements and the final silicon are presented.
Journal: IEEE Transactions on Very Large Scale Integration Systems - VLSI , vol. 19, no. 12, pp. 2339-2342, 2011
Cumulative Annual
View Publication
The following links allow you to view full publications. These links are maintained by other sources not affiliated with Microsoft Academic Search.
Share this on