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Charge-Trapping-Induced Parasitic Capacitance and Resistance in SONOS TFTs Under Gate Bias Stress

Charge-Trapping-Induced Parasitic Capacitance and Resistance in SONOS TFTs Under Gate Bias Stress,10.1109/LED.2010.2095819,IEEE Electron Device Letter

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Charge-Trapping-Induced Parasitic Capacitance and Resistance in SONOS TFTs Under Gate Bias Stress  
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This letter investigates the charge-trapping-induced parasitic resistance and capacitance in silicon-oxide- nitride-oxide-silicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in OFF-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.
Journal: IEEE Electron Device Letters - IEEE ELECTRON DEV LETT , vol. 32, no. 3, pp. 321-323, 2011
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