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Designing and Analysis of 8 Bit SRAM Cell with Low Subthreshold Leakage Power

Designing and Analysis of 8 Bit SRAM Cell with Low Subthreshold Leakage Power

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Designing and Analysis of 8 Bit SRAM Cell with Low Subthreshold Leakage Power  
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The power consumption is major concern in Very Large Scale Integration (VLSI) circuit design and reduce the power dissipation is challenging job for low power designers. . International technology roadmap for semiconductors (ITRS) reports that "leakage power dissipation" may come to dominate total power consumption. The sub-threshold leakage power is the main reason to increase the leakage power. So there is some techniques to reduce this leakage power like sleep approach, stack & some new techniques like, sleepy-stack, leakage feedback approach and sleepy keeper techniques which reduces leakage current while saving exact logic state. As the technology increases integration density of transistors increases, power consumption has become a major concern in today's processors and SoC designs. Considerable attention has been paid to the design of low power and high-performance SRAMs as they are critical components in both handheld devices and high performance processors. In this paper we design 8 bit S-RAM by using the leakage current reduction techniques. The proposed circuits were designed in 0.18µm CMOS/VLSI technology with-in Micro-Wind tool, and measure power consumption for design approaches, and we achieves up to nearly 50% less power consumption than existing basic SRAM.
Published in 2012.
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