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Power characterisation for the fabric in fine-grain reconfiguralbe architectures

Power characterisation for the fabric in fine-grain reconfiguralbe architectures,10.1109/SPL.2009.4914910,Tobias Becker,Peter Jamieson,Wayne Luk,Peter

Power characterisation for the fabric in fine-grain reconfiguralbe architectures   (Citations: 2)
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This paper proposes a methodology for characterising power consumption of the fine-grain fabric in reconfigurable architectures. It covers active and inactive power as well as advanced low-power modes. A method based on random number generators is adopted for comparing activity modes. We illustrate our approach using four field-programmable gate arrays (FPGAs) that span a range of process technologies: Virtex-II Pro, Spartan-3E, Spartan-3AN, and Virtex-5. We find that, despite improvements through process technology and low-power modes, current devices need further improvements to be sufficiently power efficient for mobile applications.
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