Automatic gate-level synthesis of speed-independent circuits
In this paper, we present a CAD tool for the synthesis of asynchronous control circuits using basic gates such as AND gates and OR pates. The svnthesized circuits are soeed-indeoendent: that is, &ey work correctly regardless of &dividual ‘gate de: lays. We present synthesis results for a variety of specifications taken from industrv and oreviouslv oublished examoles. We compare our speed&iep&dent c&its with those n&-speedindepedent circuits synthesized using the algorithms described in [I], in which delay elements are a&led to remove circuit hazards. These synthesis results show that our circuits are on average approximately 25% faster with an area penalty of only 15%. This work demonstrates that direct synthesis of gate-level speed-independent circuits is not only feasible, but also produces robust and relatively efticient circuits compared to those synthesized with timing constraints.