<?xml version="1.0" encoding="utf-8"?><rss version="2.0"><channel><title>RSS for High performance wafer level underfill material with high filler loading</title><link>http://academic.research.microsoft.com/Rss.aspx?cata=9&amp;id=51060628</link><description>Search RSS feed for Microsoft Academic Search</description><generator>MSRA Libra RSS Burner</generator><copyright>(c)2008 Microsoft Corpration, All right reserved.</copyright><pubDate>Thu, 20 Jun 2013 10:20:22 GMT</pubDate><lastBuildDate>Thu, 20 Jun 2013 10:20:22 GMT</lastBuildDate><category /><item><title>High performance wafer level underfill material with high filler loading</title><link>http://academic.research.microsoft.com/Publication/51060628</link><pubDate>Thu, 20 Jun 2013 03:20:22 GMT</pubDate><guid isPermaLink="false">510606281</guid><description><![CDATA[<div><a href="http://academic.research.microsoft.com/Author/22379438">Satoru Katsurayama</a>, <a href="http://academic.research.microsoft.com/Author/13351588">Hiroshi Suzuki</a>, <a href="http://academic.research.microsoft.com/Author/114862">Jae-Woong Nah</a>, <a href="http://academic.research.microsoft.com/Author/1672266">Michael Gaynes</a>, <a href="http://academic.research.microsoft.com/Author/3548260">Claudius Feger</a>:
            
            <span style="margin-left:20px">(Citations:1)</span><span style="margin-left:20px"><a href="http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=05898540">view publication</a></span></div><div>A new wafer level underfill material with filler content of 60 weight % was developed for <a href='http://academic.research.microsoft.com/Keyword/18101/high-performance'>high performance</a>  <a href='http://academic.research.microsoft.com/Keyword/54166/flip-chip'>flip chip</a>  applications with lead free solder bumps. Systematic optimization of the viscosity behavior led to good spin coat ability even for the material with high filler loading. The material can be applied onto the bumped wafer with high uniformity up to a thickness of 100 m by spin coating. The thickness variation was less than 5%. Additionally, void reduction in the package was realized by optimizing the curing process. By controlling the viscosity during the postcuring step voids in the package can be eliminated. Finally, the package with the new wafer level underfill material exhibited good reliability including during thermal cycling.</div><div>Conference: <a href="http://academic.research.microsoft.com/Conference/3695">Electronic Components and Technology Conference - ECTC</a>, pp. 370-374, 2011</div><div></div><div />]]></description></item></channel></rss>