A 64-Gb MLC (2 bit/cell) NAND flash memory with the highest memory density to date as an MLC flash memory, has been successfully developed. To decrease the chip size, 2-physical-plane configuration with 16 KB wordline-length, a new bit-line hook-up architecture, and a top-metal-congestion-free optimized peripheral circuit floor plan, are introduced. ...

An Itanium® processor implemented in 32 nm CMOS with nine layers of Cu contains 3.1 billion transistors. The die measures 18.2 mm by 29.9 mm. The processor has eight multi-threaded cores, a ring based system interface and combined cache on the die is 50 MB. High-speed links allow for peak processor-to-processor bandwidth of ...

This paper describes a tri-modal asymmetric bidirectional differential memory interface that supports data rates of up to 20 Gbps over 3” FR4 PCB channels while achieving power efficiency of 6.1 mW/Gbps at full speed. The interface also accommodates single-ended standard DDR3 and GDDR5 signaling at 1.6-Gbps and 6.4-Gbps operations, respectively, without package ...

In this paper, we present a low-power high-performance WiMAX chipset fully compliant with IEEE 802.16e specification corrigendum 1, 2 for mobile broadband access and WiMAX Forum system profile Wave2. The chipset is comprised of a 632.7-mW/24.99-${\hbox {mm}}^{2}$ modem/router chip and a 364-mW/11.05- ${\hbox {mm}}^{2}$ dual-band ...

This paper presents a tri-modal asymmetric memory controller interface that achieves 12.8-Gbps single-ended (SE) signaling over $3^{\prime\prime}$ stripline FR4 traces. The controller can be configured to communicate with commercially available GDDR5 and DDR3 memories at 6.4 and 1.6 Gbps, respectively, with no package change. The interface is equipped with a compact voltage-...

We present a complete signal generator with integrated digital-to-analog convertor (DAC) on a chip which can generate complex waveforms at up to 7.2 GSa/s with 14 bit resolution or at up to 12 GSa/s with 12 bit resolution. The 3 dB bandwidth is 4.4 GHz. The chip includes digital signal processing (DSP) logic for ...

A monolithic 64 Gb MLC NAND flash based on 21 $~$nm process technology has been developed. The device consists of 4-plane arrays and provides page size of up to 32 KB. It also features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s. To improve performance and reliability, on-chip ...

A 1.2 V 1 Gb mobile SDRAM, having 4 channels with 512 DQ pins has been developed with 50 nm technology. It exhibits 330.6 mW read operating power during 4 channel operation, achieving 12.8 GB/s data bandwidth. Test correlation techniques to verify functions through micro bumps and test pads have been developed. Block based dual period ...

This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm$^{2}$ containing an estimated 1.4 billion transistors. The core and chip design methodology ...

Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold $(V_{T})$ variation, already a significant issue in today's advanced process technologies, and further exacerbated at low voltages, complicate the task of ...

This paper presents new image sensors with multi- bucket pixels that enable time-multiplexed exposure, an alternative imaging approach. This approach deals nicely with scene motion, and greatly improves high dynamic range imaging, structured light illumination, motion corrected photography, etc. To implement an in-pixel memory or a bucket, the new image sensors incorporate the virtual phase CCD concept into ...

The digital delay-locked loop (DLL) with racing mode and the countered column address strobe (CAS) latency controller are proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power consumption, low jitter, fast locking, wide range of locking, and stuck-free control. The merged dual coarse delay line (MDCDL) reduces the dynamic power ...

AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay $({\rm T}_{\rm CRIT})$. The UDL can be used in any product without any need for customizing. In addition, averaging the results ...

This paper presents a chipset aiming at high resolution imaging systems for real-time people screening applications operating near the W-band. The frequency of operation ranges from 70 GHz to 82 GHz for optimal image resolution and depth of focus. The frequency generation for both receiver and transmitter chips consists of a mixer based frequency quadrupler with an input ...

A dual-loop architecture employs eight distributed microregulators (UREGs) to achieve load response times below 500 ps in 45-nm SOI CMOS. The trip point of an asynchronous comparator inside each UREG is tuned for high DC accuracy with a local charge pump, which receives UP/DOWN currents from a slow outer feedback loop. The feedback through the charge pumps ...

This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated ...

The first AMD Fusion™ accelerated processing unit (APU), code-named “Zacate,” incorporates a pair of Bobcat x86 processors, a 1 MB L2 cache, an AMD Radeon™ 6310 DirectX®11 GPU with 80 stream processors, a media accelerator, an integrated NorthBridge (NB), integrated DisplayPort, LVDS, and VGA display interfaces, a PCIe® Gen1 or Gen2 I/O interface, and a single 64-...

This paper presents the design and implementation of a high-performance fully-digital PWM DAC and switching output stage which can drive a speaker in portable devices, including cellular phones. Thanks to the quaternary pulse-width modulation scheme, filter-less implementation are possible. A pre-modulation DSP algorithm eliminates the harmonic distortion inherent to the employed modulation process, and an ...

This paper describes the second-generation Intel Core processor, a 32-nm monolithic die integrating four IA cores, a processor graphics, and a memory controller. Special attention is given to the circuit design challenges associated with this kind of integration. The paper describes the chip floor plan, the power delivery network, energy conservation techniques, the clock generation and distribution, the ...

This paper describes key circuit innovations in a new x86-64 micro-architecture AMD code-named “Bulldozer” , . It is implemented in 32 nm high-K metal gate SOI CMOS. It occupies 30.9 mm $^{2}$, contains 213 million transistors, reduces the number of F04 gates per cycle by more than 20% compared to a previous processor in the same technology , ...

This paper proposes schemes for the direct measurement of bit-line (BL) voltage swing, sense amplifier (SA) offset voltage, and word-line (WL) pulse width, demonstrated in a 40 nm CMOS 32 kb fully functional SRAM macro with $< $2% area penalty. This is the first such scheme to enable the optimal tuning of WL-pulse (WLP) width according to ...

A low-power receiver circuit in 32 nm SOI CMOS is presented, which is intended to be used in a source-synchronous link configuration. The design of the receiver was optimized for power owing to the assumption that a link protocol enables a periodic calibration during which the circuit does not have to deliver valid data. In addition, it is ...

A 1.5 V low-power stereo audio codec in 0.13 $\mu$m CMOS is described. The microphone path includes a programmable gain stage with an enhanced transconductance cell followed by a continuous-time $\Sigma \Delta $ ADC with capacitive feed-forward and capacitive direct feedback. The speaker path employs a 1 mA Class-AB speaker amplifier with an improved ...

A 64 Mb SRAM macro has been fabricated in a 32 nm high-k metal-gate SOI technology. The SRAM features a 0.154 $\mu\hbox{m}^{2}$ bit-cell, the smallest to date for a 32 nm SOI product. A 0.7 V ${\rm VDD}_{\rm MIN}$ operation is enabled by three assist features. Stability is improved by a ...

A source synchronous I/O system based on high-density silicon carrier interconnects is introduced. Benefiting from the advantages of advanced silicon packaging technologies, the system uses 50 $\mu$m-pitch $\mu$C4s to reduce I/O cell size and fine-pitch interconnects on silicon carrier to achieve record-breaking interconnect density. An I/O architecture is introduced with link ...

This paper describes the design topologies and considerations of a differential sinusoidal-output digitally controlled crystal oscillator (DCXO) intended for use in cellular applications. The oscillator has a fine-tuning range of ${\pm}$44 ppm, approximately 14 bits of resolution, and an average step size of 0.005 ppm. All signals connecting externally to I/O pins are sine waves ...

This paper proposes a 55 nm CMOS 12-bit current-steering video digital-to-analog converter (DAC) directly powered by the single-inductor dual-output (SIDO) switching converter to compose a dynamic voltage scaling (DVS) system and improve the power efficiency. Dual-DVS control in both digital and analog circuits can effectively reduce power consumption. With various supply voltages, the ...

A power and area efficient sensor interface consumes 6.4 mW from 1.2 V while occupying 5 mm$\,\times\,$ 5 mm in 0.13 $\mu$ m CMOS. The interface offers simultaneous access to 96 channels of broadband neural data acquired from cortical microelectrodes as part of a head-mounted wireless recording system, enabling basic neuroscience as well as neuroprosthetics ...

A low temporal noise and high dynamic range CMOS image sensor is developed. A 1Mpixel CMOS image sensor with column-parallel folding-integration and cyclic ADCs has 80$~\mu\hbox{V}_{\rm rms}~(1.2{\rm e}^{-})$ temporal noise, 82 dB dynamic range using 64 samplings in the folding-integration ADC mode. Very high variable gray-scale resolution of 13b ...

A 12-bit 3 GS/s 40 nm two-way time-interleaved pipeline analog-to-digital converter (ADC) is presented. The proposed adaptive power/ground architecture eliminates the headroom limitations due to the deeply scaled power supply in nanometer CMOS technologies, while preserving the intrinsic speed of thin-oxide MOSFETs with minimum channel length for key analog blocks. Moreover, in ...

We report on the design and characterization of a novel time-resolved image sensor fabricated in a 130 nm CMOS process. Each pixel within the 32$\times$32 pixel array contains a low-noise single-photon detector and a high-precision time-to-digital converter (TDC). The 10-bit TDC exhibits a timing resolution of 119 ps with a timing ...

A silicon integrated LNA for WCDMA cellular infrastructure applications, e.g., base stations will be demonstrated. The LNA is designed for WCDMA band II, i.e., 1.92–1.98 GHz, and reaches a 0.9 dB NF at 27 $^{\circ}$C and 1.2 dB at 65 $^{\circ}$C. A 0.1 dB NF improvement is obtained when the ...

A 512 Mbit consumer DDR2 SDRAM that uses self-dynamic voltage scaling (SDVS) and adaptive design techniques is introduced in this paper. With the increase in the significance of process variation, higher performance requirements reduce the allowable design margin in DRAM circuits. However, self-dynamic voltage scaling gives a greater timing margin in the circuitry by changing the internal supply ...

A battery-free nano-power buck converter with a proposed dynamic on/off time (DOOT) control can achieve high conversion efficiency over a wide load range. The DOOT control can predict the on/off time at different input voltages without a power consuming zero current detection (ZCD) circuit, as well as suppress static power in idle periods. To adapt to ...

In this paper, a linear CMOS power amplifier (PA) with high output power (34-dBm saturated output power) for high data-rate mobile applications is introduced. The PA incorporates a parallel combination of four differential PA cores to generate high output power with good efficiency and linearity. To implement an efficient on-chip power combiner in a small form-factor, ...

This paper introduces a fully-integrated wireline transceiver operating at 40 Gb/s. The transmitter incorporates a 5-tap finite-inpulse response (FIR) filter with LC-based delay lines precisely adjusted by a closed-loop delay controller. The receiver employs a similar 3-tap FIR filter as an equalizer front-end with digital adaptation, and a sub-rate clock and ...

A low-distortion third-order class-D amplifier that is fully integrated into a 0.18-$\mu$ m CMOS process was designed for direct battery hookup in a mobile application. A class-D amplifier for direct battery hookup must have a sufficiently high power supply rejection ratio (PSRR) in preparation for noise, such as when a global system for mobile ...

Journal: IEEE Journal of Solid-state Circuits - IEEE J SOLID-STATE CIRCUITS, 2012]]>http://academic.research.microsoft.com/Publication/56946770Mon, 20 May 2013 00:46:35 GMT56946770Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsuview publication

Journal: IEEE Journal of Solid-state Circuits - IEEE J SOLID-STATE CIRCUITS, vol. 47, no. 1, pp. 3-7, 2012]]>http://academic.research.microsoft.com/Publication/57012521Mon, 20 May 2013 00:46:34 GMT57012521Ewout Martens, André Bourdoux, Aissa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaertview publication

A fourth-order continuous-time RF bandpass $\Delta\Sigma$ ADC has been fabricated in 40 nm CMOS for $f_s/4$ operation around a 2.22 GHz central frequency. A complete system has been implemented on the test chip including the ADC core, the fractional-N PLL with clock generation network, and the digital decimation filters and downconversion (DFD). The ...

A compact and robust magnetic label detector for biomedical assays is implemented in 0.18-$\mu$ m CMOS. Detection relies on the magnetic relaxation signature of a microbead label for improved tolerance to environmental variations and relaxed dynamic range requirement, eliminating the need for baseline calibration and reference sensors. The device includes embedded electromagnets to eliminate external magnets and reduce ...

This paper describes the design and measured performance of three different silicon photonic switches: a 2$\,\times\,$ 2 switch, a 1$\,\times\,$ 2 switch, and a 4$\,\times\,$ 4 switch. All of the devices have been hybrid integrated with a corresponding custom 90-nm CMOS driver. The 2 $\,\times\,$2 switch is based on a wavelength-insensitive Mach–Zehnder interferometer (...

A transformer-combined fully integrated outphasing class-D PA in 45 nm LP CMOS achieves 31.5 dBm peak output power at 2.4 GHz with 27% peak PAE, and supports over 86 dB of output power range. The PA employs dynamic power control (DPC) whereby sections of the PA are turned on or off dynamically according to the instantaneous ...

A 10-b 320-MS/s pipeline analog-to-digital converter (ADC) with low dc gain opamps, as low as 30.6 dB based on simulations, in its multiplying digital-to-analog converters (MDACs) is presented. A foreground self-calibration technique is proposed to reduce stage gain error by adjusting feedback factor with a calibration capacitor array. The prototype in ...

On-chip DC-DC converters have the potential to offer fine-grain power management in modern chip-multiprocessors. This paper presents a fully integrated 3-level DC-DC converter, a hybrid of buck and switched-capacitor converters, implemented in 130 nm CMOS technology. The 3-level converter enables smaller inductors (1 nH) than a buck, while generating a wide range ...

We apply the “assisted opamp technique” to the design of a 1 GS/s single-bit continuous-time $\Delta\Sigma$ modulator (CTDSM) that achieves 10 bit resolution in 15.625 MHz bandwidth. The enhanced linearity and speed of the first integrator of the modulator, necessitated by single-bit operation, are obtained in a power efficient manner using opamp assistance. However, ...

This paper presents the design and measurement of a 4 $\times$ oversampled 18th order digital low-pass FIR filter. It is a key building block in the proposed digitally enhanced transmitter architecture for 60 GHz wireless high-data rate links. Spectrum mask requirements are fully satisfied for OFDM modulated signals without requiring additional analog filtering. Pipelined CPL adders and TSPC ...

In the framework of MOSFET reliability for RF/AMS applications, a deep investigation of RF parameters degradation is performed. An innovative flow, composed of DC and RF stresses with DC and RF aging characterization, is presented. Degradation kinetics of main parameters are physically explained and modeled using PSP compact model to predict the behavior of stressed devices.

This paper presents an energy-efficient capacitive-sensor interface with a period-modulated output signal. This interface converts the sensor capacitance to a time interval, which can be easily digitized by a simple digital counter. It is based on a relaxation oscillator consisting of an integrator and a comparator. To enable the use of a current-efficient telescopic OTA in ...

This paper presents an integrated neural stimulator with highly efficient and flexible frontend which is intended for an epiretinal implant with 1024 electrodes. It features programmable stimulation pulse shapes, a high-voltage (HV) output driver with compliance monitor for supply voltage adaptation, active and passive charge balancers, and electrode impedance measurement. Area and power efficiency is achieved by global timing ...

A 100-V ac energy meter based on the system-on- a-film (SoF) concept, in which various devices are integrated on a flexible film, is presented. The system consists of 20-V organic CMOS digital and analog circuits with a floating gate (FG) for process variation compensation, 100-V organic pMOS rectifiers for generating a 50-Hz clock and ...

A 3.3 V 6-bit binary-weighted current-steering digital-to-converter converter (DAC) using low-voltage organic p-type thin-film transistors (OTFTs) is presented. The converter marks records in speed and compactness owing to an OTFT fabrication process that is based on high-resolution silicon stencil masks. The chip has been fabricated on a glass substrate and ...

The dual-band recording of the local-field potential (LFP, 0.1–200 Hz) and the spike potential (SP, 200 Hz–10 kHz) is important for physiological studies at the cellular level. Recent study shows that the LFP signal plays important roles in modulating many profound cellular mechanisms. Although various bio-signal acquisition circuits have been reported over the years, ...

This paper proposes a design approach targeting circuits operating at extremely low supply voltages, with the goal of reducing the voltage at which energy is minimized, thereby improving the achievable energy efficiency of the circuit. The proposed methods accomplish this by minimizing the circuit's ratio of leakage to active current. The first method, super pipelining, increases the number of ...

This paper presents a noninvasive wireless sensor platform for continuous health monitoring. The sensor system integrates a loop antenna, wireless sensor interface chip, and glucose sensor on a polymer substrate. The IC consists of power management, readout circuitry, wireless communication interface, LED driver, and energy storage capacitors in a 0.36- ${\hbox {mm}}^{2}$ CMOS chip with no external components. ...

In this work, we have demonstrated a fully-integrated, high-efficiency CMOS inverse Class-D PA. Such efficient switching amplifiers can form the core of mixed-signal polar transmitters. A comprehensive analytical framework has been developed to determine optimum component values to maximize efficiency. Operating from a 1-V supply, the PA achieves a peak efficiency of 44% without any ...

This paper presents a 95 mV startup-voltage step-up DC-DC converter for energy harvesting applications. The capacitor pass-on scheme enables operation of the system from an input voltage of 95 mV without using additional off-chip components. To compensate for the die-to-die process variation, post-fabrication threshold voltage $({\rm V}_{\rm TH})$ trimming is applied ...

A reconfigurable bandpass continuous-time $\Sigma \Delta$ RF ADC tunable over the 0.8–2 GHz frequency range is presented. System- and circuit-level innovations provide low power consumption and reduced circuit complexity. The proposed architecture operates in both the first- and second-Nyquist zones to enable a wide tuning range from a fixed sampling frequency of 3.2 GHz. ...

This paper reports on the demonstration of series tuning for lateral micromechanical oscillators and its application for electronic temperature compensation of piezoelectric lateral bulk acoustic resonator (LBAR) micromechanical oscillators. Two aluminum nitride-on-silicon (AlN-on-Si) piezoelectric LBARs, one operating at 427 MHz $({R}_{m} \approx 180~\Omega,~{\rm Q}_{\rm unloaded} \approx 1400)$ and the other operating at ...

A 1920$\,\times\,$ 1080 160$^{\circ}$ object viewpoint recognition system-on-chip (SoC) is presented in this paper. The SoC design is dedicated to wearable vision applications, and we address several crucial issues including the low recognition accuracy due to the use of low resolution images and dramatic changes in object viewpoints, and the high power consumption caused by the ...

This paper presents a fully digital polar up-converter for wireless transmission in the GHz range. The system is designed to drive two class-E power amplifiers (PAs) with a power combiner. It uses baseband pulse width modulation (PWM) for the amplitude modulation (AM), whereas phase modulation (PM) is implemented by shifting the RF carrier in time. Both the PWM ...

The isolation techniques against substrate noise coupling utilizing through silicon via (TSV) process are described. The trench shape TSV encloses the RF circuit on a SoC chip to improve the isolation between digital circuits and the RF circuits without constraints of on-chip interconnect above first metal as the TSV is connected to the grounded 1st metal from the back ...

A small-size on-chip transformer-based digital isolator for power control systems is proposed. With a proposed pulse generation and detection scheme that enables a 5 V standard CMOS transistor to utilize GHz-band signals, transformer area is reduced to 1/4–1/8 that of conventional transformers. A test chip achieves a 2.5 kV isolation voltage, a ...

We present an ultra-wideband transceiver designed for ultra-low-power communication at sub-10 cm range. The transceiver operates at a 5.6 GHz carrier frequency, chosen to minimize path loss when using a 1 cm $^{2}$ antenna, and can switch its architecture between self-synchronous rectification and low-IF to adapt its power consumption to the channel characteristic ...

An improved architecture of polar transmitter (TX) is presented. The proposed architecture is digitally-intensive and mainly composed of an all-digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma ΔΣ modulator for envelop modulation, and a H-bridge class-D power amplifier (PA) for differential signaling. The ΔΣ modulator is clocked using the phase modulated ...

A 59-GHz push-push voltage-controlled oscillator (VCO)—based on 0.18-$\mu$m SiGe BiCMOS technology—for a full-band 60-GHz transceiver was developed. The VCO uses a loop-ground transmission line (LG-TML) composed of $\lambda _{{\rm f}0} /2$ signal lines (half wavelength at fundamental frequency) and $\lambda _{2{\rm f}0} /4$ secondary lines (...

An Li-ion battery charger based on a charge-control buck regulator operating at 2.2 MHz is implemented in 180 nm CMOS technology. The novelty of the proposed charge-control converter consists of regulating the average output current by only sensing a portion of the inductor current and using an adaptive reference voltage. By adopting this approach, the charger ...

A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that ...

The developed associative-memory architecture utilizes a mapping operation of the Hamming distances into frequency space with ring oscillators programmable in discrete frequency steps. As a result fast word-parallel search of the nearest Hamming distance with low power consumption is obtained. Additionally, high robustness against fabrication-related variations of the MOSFET characteristics is achievable by design because the size ...

An embedded DRAM using a standard NAND flash memory process has been demonstrated for the first time. This embedded DRAM without extra costly manufacturing process realizes 2.4 mm$^{2}$ /Mb macro density and provides large-capacity on-chip page buffers and data caches for NAND flash memories to enhance their performances. A 32 KB DRAM buffer macro with 1....

A 30-MHz–2.4-GHz complementary metal oxide semiconductor (CMOS) receiver with an integrated tunable RF filter and a dynamic-range-scalable energy detector for both white-space and interference-level sensing in cognitive radio systems is reported. The second-order RF filter has only two stacked transistors, and its use, in combination with a subsequent harmonic rejection mixer, ...

This paper proposes a 1-A, 6.4-MHz switching frequency DC-DC converter with embedded digital controller, implemented in 65-nm CMOS technology. The proposed DC-DC converter, exploiting a customized, multi-function SAR ADC and a non-linear PID controller, can switch automatically between continuous-conduction mode and pulse-skipping mode, thus maintaining a fairly large efficiency also ...

In this paper, a charge-balancing accelerometer is presented. A hybrid interface topology is utilised to achieve high resolution, high linearity and low power supply sensitivity. The accelerometer consists of a micromechanical sensor element, a self-balancing bridge (SBB) open-loop readout, AC force feedback and $\Delta \Sigma$ ADC. The SBB converts acceleration to ratiometric voltage. The ratiometric output of ...

In this paper a class-D audio amplifier for mobile applications is presented realized in a 0.14 $\mu\hbox{m}$ CMOS technology tailored for mobile applications. The amplifier has a simple PDM-based digital interface for audio and control that requires only two pins and enables assembly in 9-bump WL-CSP. The complete audio path is discussed that ...

Abstract: Firms operate in a complex economic environment where they interact with a broad base of stakeholders. Stakeholders are interested in the economic environment of the firm and its prospects to determine the value of their claims. For this valuation a wide range of information sources is used which per definition provide a depiction of the firm and its economic ...

Abstract: This doctoral thesis focuses on two topics that have received considerable attention from academics, regulators, and the business press over the past decades: insider trading, and shareholder activism. The first chapter evaluates proxy proposals as a corporate governance device in Europe. The second chapter analyzes the relation between firm-level corporate governance rules and the profitability of insider trading. ...

Journal: IEEE Journal of Solid-state Circuits - IEEE J SOLID-STATE CIRCUITS, 2012]]>http://academic.research.microsoft.com/Publication/56946764Mon, 20 May 2013 00:45:56 GMT56946764Joonsung Bae, Kiseok Song, Hyungwoo Lee, Hyunwoo Cho, Hoi-Jun Yooview publication

An energy-efficient wireless body-area-network (WBAN) transceiver is implemented in 0.18-$\mu$ m CMOS technology with 1-V supply voltage. For the low energy consumption, the body channel communication (BCC) PHY is utilized with the theoretical results of Maxwell's equation analysis behind the BCC. Based on the channel analysis, the resonance matching (RM) and contact impedance ...

We present an area-efficient neural signal-acquisition system that uses a digitally intensive architecture to reduce system area and enable operation from a 0.5 V supply. The architecture replaces ac coupling capacitors and analog filters with a dual mixed-signal servo loop, which allows simultaneous digitization of the action and local field potentials. A noise-efficient DAC topology ...

A digitally-controlled polar transmitter with a watt-class CMOS power amplifier is demonstrated, implemented in a 0.15 $\mu{\hbox {m}}$ RF CMOS process. Stacked FETs in a current-mode class-D configuration are used to obtain high breakdown voltage and high efficiency in the output stage, and a doughnut-shaped Guanella reverse balun is applied to achieve a ...

This paper presents an automatic gain control (AGC) amplifier with temperature compensation for high-speed applications. The proposed AGC consists of a folded Gilbert variable gain amplifier (VGA), a dc offset canceller, inductorless post amplifiers, a linear open-loop peak detector (PD), an integrator, a symmetrical exponential voltage generator, and a compensation block for temperature stability. The novel temperature compensation ...

Many mobile SoC chips employ a “two-macro” approach including volatile and nonvolatile memory macros (i.e. SRAM and Flash), to achieve high-performance or low-voltage power-on operation with the capability of power-off nonvolatile data storage. However, the two-macro approach suffers from slow store/restore speeds due to word-by-word serial transfer of data between ...

Event-Driven vision sensing is a new way of sensing visual reality in a frame-free manner. This is, the vision sensor (camera) is not capturing a sequence of still frames, as in conventional video and computer vision systems. In Event-Driven sensors each pixel autonomously and asynchronously decides when to send its address out. This way, the sensor output ...

Frequency synthesizers based on sub-harmonic injection-locked oscillators can reduce power and area effectively. However, they suffer from unwanted side-bands caused by undesirable harmonics in the injection pulse. This paper presents a pulse shaping technique that reduces these undesirable harmonics in the injection pulse and produces low-spur synthesized output. The robustness of the proposed technique and the ...

A wideband digital RF receiver front-end employing a discrete-time (DT) filter is presented for application to m-WiMAX (WiBro). By employing a sampling mixer and a DT filter, the receiver operates in the charge domain. In addition to the flexibility of the DT filter, the new non-decimation finite impulse response (NDF) filter can be cascaded to a ...

Among all the emerging memories, Spin-Transfer Torque Random Access Memory (STT-RAM) has demonstrated many promising features such as fast access speed, nonvolatility, excellent scalability, and compatibility to CMOS process. However, the large process variations of both magnetic tunneling junction (MTJ) and MOS transistors in the scaled technologies severely limit the yield of STT-RAM chips. In this work, ...

In the effort to achieve low access energy non-volatile memory, challenges are encountered in sensing data at low power supply voltage. This work presents the design of a ferroelectric random access memory (FRAM) as a promising candidate for this need. The challenges of sensing diminishingly small charge and developing circuits compatible with the scaling of FRAM technology to low ...

This paper presents a wideband blocker filtering technique for an RF front-end. A wideband LNA and a transferred impedance filter are implemented as part of a receiver to demonstrate the feasibility of the system. The transferred impedance filter includes an adjustable polyphase filter to compensate for the phase shift in the system in order to maintain correct operating frequency. ...

A voltage scalable zero-crossing based (ZCB) pipelined ADC built in 65 nm CMOS is described. The highly digital implementation characteristic of the ZCB circuit technique enables energy efficient operation and supply voltage scaling. Several new techniques including the unidirectional coarse-fine charge transfer scheme, programmable ramp rates, and flash resistor ladder scaling, are developed to allow efficient operation at ...

In this paper we will present a low-phase-noise wide-tuning-range oscillator suitable for scaled CMOS processes. It switches between the two resonant modes of a high-order LC resonator that consists of two identical LC tanks coupled by capacitor and transformer. The mode switching method does not add lossy switches to the resonator and thus doubles frequency ...

This paper presents a low-power mixed-signal adaptive 60 GHz baseband in 65 nm CMOS. The design integrates variable gain amplifiers, analog phase rotator, 40-coefficient I/Q decision feedback equalizers (DFEs), clock generation and data recovery circuits, and adaptation hardware. The baseband achieves 10 Gb/s operation with ${\rm BER}<10^{-12}$ while consuming 53 mW (adaptation ...

An improved envelope amplifier architecture for envelope tracking RF power amplifiers is presented, consisting of two switching amplifiers and one linear amplifier. The first switching amplifier and the linear amplifier provide wideband and high-efficiency operation, while the second switching amplifier provides a reduced bandwidth variable supply to the linear amplifier to further reduce power loss. The first switching amplifier ...

This paper presents a multimode FFT processor for wireless personal area network (WPAN), wireless local area network (WLAN), and wireless metropolitan area network (WMAN) applications. Using the proposed flexible-radix-configuration multipath-delay-feedback (FRCMDF) architecture, variable-length/multiple-stream FFTs capable of achieving a high throughput can be performed in a hardware-efficient manner. Based on the FRCMDF structure, ...

This paper reports on efficient interfacing of typical vibration-driven electromagnetic transducers for micro energy harvesting. For this reason, an adaptive charge pump for dynamic maximum power point tracking is compared with a novel active full-wave rectifier design. For efficient ultra-low voltage rectification, the introduced active diode design uses a common-gate stage in conjunction with supply-independent ...

A fully-integrated, silicon photonic transceiver is demonstrated in a silicon-on-insulator process using photonic microring resonator modulators for low power consumption. The trade-offs between bandwidth and extinction ratio are discussed and motivate the use of transmit pre-emphasis for ring modulators to increase the interconnect data rate. The transmitter and receiver is demonstrated to data rates of ...

We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. For sake of ...

A 100 W, 5.1-channel, single-chip, digital-input class-D audio amplifier with a low-voltage (LV) digital circuit and high-voltage (HV) switching power stage is designed for moderate-performance and cost-effective speaker systems. The LV portion, including multi-channel audio processors, delta-sigma modulators (DSMs), and pulse-width modulation (PWM) generators, is implemented with a ...

Circuit techniques for enhancing the retention time and random cycle of logic-compatible embedded DRAMs (eDRAMs) are presented. An asymmetric 2T gain cell utilizes the gate and junction leakages of a PMOS write device to maintain a high data ‘1’ voltage level which enables fast read access using an NMOS read device. A current-mode sense amplifier (C-S/A) ...

Implementing serial I/O receivers based on analog-to-digital converters (ADCs) and digital signal post-processing has drawn growing interest with technology scaling, but power consumption remains among the key issues for such digital receiver in high speed applications. This paper presents an ADC-based receiver that uses a low-gain analog and mixed-mode pre-equalizer in conjunction ...

This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal charge redistribution DAC employs unit capacitance of 0.5 fF and ...