-
...this paper presents two new algorithms, redundant vec- tor elimination (rve) and essential fault reduction (efr), for generating compact test sets for combinational circuit s under the single stuck...efr), and a new heuristic for estimating the minimum single stuck at fault test set size. these algorithms and the dynamic compaction algorithm proposed in (6) are incorpor...
-
...this paper presents a new algorithm, essential fault reduction (efr), for generating compact test sets for combinationalcircuits under the single stuck-at fault model, and a new heuristic for estimating the minimum single stuck-at fault test set size. thesealgorithms together with the dynamic compaction algorithm are incorporated into an advanced...
-
...this paper presents two new algorithms, redundant vector elimination (rve) and essential fault reduction (efr), for generating compact test sets for combinational circuits under the single stuck at fault model, and a new heuristic for estimating the minimum single stuck at fault test set size. these algorithms together with the dynamic compaction algorithm are incorporated into an advanced...
-
...transferred to the chip under test during test application. therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce...two new tvd based static compaction algorithms are presented. experimental results for benchmark circuits demonstrate the effectiveness of the two new static compaction algorithms....
-
...during the simulation of a test set for a sequential circuit. re-visiting a state implies...consistently results in significantly higher compaction in short execution times. keywords: static test set compaction, support sets, recurrence subsequence, atpg...
-
...stuck-at faults in practical test lengths. a deterministic test set generated for the reduced circuit obtained by combining inputs into test signals is usually more compact...and performance penalty to the circuit under test. results also show that the memory storage and test application time for external testing using deterministic test sets can be reduced by as...
-
...aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. the heuristics can be added to existing test pattern generators without compromising fault...
-
...the seed selection and consequent test sequence optimization algorithms. this paper proposes a novel efficient reseeding optimization algorithm that is based on test compaction techniques for sequential designs. the proposed approach...which can provide the optimal test set compaction solution for a given test setup. alternatively, it can run for a limited time in a...
-
...it will be shown that for a class of circuits with a high fnult compatibility well-known test set compaction methods such as dynamic compaction and reverse order fault simulation...it is possible to generate test sets that are significantly smaller than test sets generated by conventional test set compaction methods. this paper will also...
-
...paper presents a high performance compact iddq test generation system for detecting bringing faults, targeting large circuits. this system is based on...two-level parallel processing technique for speeding up the test generation significantly and invoke the assist of a deterministic atpg for attaining 100% fault efficiency. the...